Using as - 8. Machine Dependent Features

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# 8. Machine Dependent Features

The machine instruction sets are (almost by definition) different on each machine where `as` runs. Floating point representations vary as well, and `as` often supports a few additional directives or command-line options for compatibility with other assemblers on a particular platform. Finally, some versions of `as` support special pseudo-instructions for branch optimization.

This chapter discusses most of these differences, though it does not include details on any machine's instruction set. For details on that subject, see the hardware manufacturer's manual.

## 8.1 ARC Dependent Features

### 8.1.1 Options

The ARC chip family includes several successive levels (or other variants) of chip, using the same core instruction set, but including a few additional instructions at each level.

By default, `as` assumes the core instruction set (ARC base). The `.cpu` pseudo-op is intended to be used to select the variant.

`-mbig-endian`
`-mlittle-endian`
  Any ARC configuration of `as` can select big-endian or little-endian output at run time (unlike most other GNU development tools, which must be configured for one or the other). Use ``-mbig-endian'` to select big-endian output, and ``-mlittle-endian'` for little-endian.

### 8.1.2 Floating Point

The ARC cpu family currently does not have hardware floating point support. Software floating point support is provided by `GCC` and uses IEEE floating-point numbers.

### 8.1.3 ARC Machine Directives

The ARC version of `as` supports the following additional machine directives:

`.cpu`
  This must be followed by the desired cpu. The ARC is intended to be customizable, `.cpu` is used to select the desired variant [though currently there are none].

## 8.2 AMD 29K Dependent Features

### 8.2.1 Options

`as` has no additional command-line options for the AMD 29K family.

### 8.2.2 Syntax

#### 8.2.2.1 Macros

The macro syntax used on the AMD 29K is like that described in the AMD 29K Family Macro Assembler Specification. Normal `as` macros should still work.

#### 8.2.2.2 Special Characters

``;'` is the line comment character.

The character ``?'` is permitted in identifiers (but may not begin an identifier).

#### 8.2.2.3 Register Names

General-purpose registers are represented by predefined symbols of the form ``GRnnn'` (for global registers) or ``LRnnn'` (for local registers), where nnn represents a number between `0` and `127`, written with no leading zeros. The leading letters may be in either upper or lower case; for example, ``gr13'` and ``LR7'` are both valid register names.

You may also refer to general-purpose registers by specifying the register number as the result of an expression (prefixed with ``%%'` to flag the expression as a register number):

    %%expression

---where expression must be an absolute expression evaluating to a number between `0` and `255`. The range [0, 127] refers to global registers, and the range [128, 255] to local registers.

In addition, `as` understands the following protected special-purpose register names for the AMD 29K family:

      vab    chd    pc0
      ops    chc    pc1
      cps    rbp    pc2
      cfg    tmc    mmu
      cha    tmr    lru

These unprotected special-purpose register names are also recognized:

      ipc    alu    fpe
      ipa    bp     inte
      ipb    fc     fps
      q      cr     exop

### 8.2.3 Floating Point

The AMD 29K family uses IEEE floating-point numbers.

### 8.2.4 AMD 29K Machine Directives

`.block size , fill`
  This directive emits size bytes, each of value fill. Both size and fill are absolute expressions. If the comma and fill are omitted, fill is assumed to be zero. In other versions of the GNU assembler, this directive is called ``.space'`.

`.cputype`
  This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.
`.file`
  This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.

  > Warning: in other versions of the GNU assembler, `.file` is used for the directive called `.app-file` in the AMD 29K support.

`.line`
  This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.
`.sect`
  This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.
`.use section name`
  Establishes the section and subsection for the following code; section name may be one of `.text`, `.data`, `.data1`, or `.lit`. With one of the first three section name options, ``.use'` is equivalent to the machine directive section name; the remaining case, ``.use .lit'`, is the same as ``.data 200'`.

### 8.2.5 Opcodes

`as` implements all the standard AMD 29K opcodes. No additional pseudo-instructions are needed on this family.

For information on the 29K machine instruction set, see Am29000 User's Manual, Advanced Micro Devices, Inc.

## 8.3 ARM Dependent Features

### 8.3.1 Options

`-marm [2|250|3|6|60|600|610|620|7|7m|7d|7dm|7di|7dmi|70|700|700i|710|710c|7100|7500|7500fe|7tdmi|8|strongarm|strongarm110]`
  This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor.
`-marmv [2|2a|3|3m|4|4t]`
  This option specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture.
`-mthumb`
  This option specifies that only Thumb instructions should be assembled.
`-mall`
  This option specifies that any Arm or Thumb instruction should be assembled.
`-mfpa [10|11]`
  This option specifies the floating point architecture in use on the target processor.
`-mfpe-old`
  Do not allow the assemble of floating point multiple instructions.
`-mno-fpu`
  Do not allow the assembly of any floating point instructions.
`-mthumb-interwork`
  This option specifies that the output generated by the assembler should be marked as supporting interworking.
`-mapcs [26|32]`
  This option specifies that the output generated by the assembler should be marked as supporting the indicated version of the Arm Procedure. Calling Standard.
`-EB`
  This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.
`-EL`
  This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor.

### 8.3.2 Syntax

#### 8.3.2.1 Special Characters

``;'` is the line comment character.

*TODO* Explain about /data modifier on symbols.

#### 8.3.2.2 Register Names

*TODO* Explain about ARM register naming, and the predefined names.

### 8.3.3 Floating Point

The ARM family uses IEEE floating-point numbers.

### 8.3.4 ARM Machine Directives

`name .req register name`
  This creates an alias for register name called name. For example:

              foo .req r0

`.code [16|32]`
  This directive selects the instruction set being generated. The value 16 selects Thumb, with the value 32 selecting ARM.
`.thumb`
  This performs the same action as .code 16.
`.arm`
  This performs the same action as .code 32.
`.force_thumb`
  This directive forces the selection of Thumb instructions, even if the target processor does not support those instructions
`.thumb_func`
  This directive specifies that the following symbol is the name of a Thumb encoded function. This information is necessary in order to allow the assembler and linker to generate correct code for interworking between Arm and Thumb instructions and should be used even if interworking is not going to be performed.
`.ltorg`
  This directive causes the current contents of the literal pool to be dumped into the current section (which is assumed to be the .text section) at the current location (aligned to a word boundary).
`.pool`
  This is a synonym for .ltorg.

### 8.3.5 Opcodes

`as` implements all the standard ARM opcodes.

*TODO* Document the pseudo-ops (adr, nop)

For information on the ARM or Thumb instruction sets, see ARM Software Development Toolkit Reference Manual, Advanced RISC Machines Ltd.

## 8.4 D10V Dependent Features

### 8.4.1 D10V Options

The Mitsubishi D10V version of `as` has a few machine dependent options.

``-O'`
  The D10V can often execute two sub-instructions in parallel. When this option is used, `as` will attempt to optimize its output by detecting when instructions can be executed in parallel.
``--nowarnswap'`
  To optimize execution performance, `as` will sometimes swap the order of instructions. Normally this generates a warning. When this option is used, no warning will be generated when instructions are swapped.

### 8.4.2 Syntax

The D10V syntax is based on the syntax in Mitsubishi's D10V architecture manual. The differences are detailed below.

#### 8.4.2.1 Size Modifiers

The D10V version of `as` uses the instruction names in the D10V Architecture Manual. However, the names in the manual are sometimes ambiguous. There are instruction names that can assemble to a short or long form opcode. How does the assembler pick the correct form? `as` will always pick the smallest form if it can. When dealing with a symbol that is not defined yet when a line is being assembled, it will always use the long form. If you need to force the assembler to use either the short or long form of the instruction, you can append either ``.s'` (short) or ``.l'` (long) to it. For example, if you are writing an assembly program and you want to do a branch to a symbol that is defined later in your program, you can write ``bra.s foo'`. Objdump and GDB will always append ``.s'` or ``.l'` to instructions which have both short and long forms.

#### 8.4.2.2 Sub-Instructions

The D10V assembler takes as input a series of instructions, either one-per-line, or in the special two-per-line format described in the next section. Some of these instructions will be short-form or sub-instructions. These sub-instructions can be packed into a single instruction. The assembler will do this automatically. It will also detect when it should not pack instructions. For example, when a label is defined, the next instruction will never be packaged with the previous one. Whenever a branch and link instruction is called, it will not be packaged with the next instruction so the return address will be valid. Nops are automatically inserted when necessary.

If you do not want the assembler automatically making these decisions, you can control the packaging and execution type (parallel or sequential) with the special execution symbols described in the next section.

#### 8.4.2.3 Special Characters

``;'` and ``#'` are the line comment characters. Sub-instructions may be executed in order, in reverse-order, or in parallel. Instructions listed in the standard one-per-line format will be executed sequentially. To specify the executing order, use the following symbols:

``->'`
  Sequential with instruction on the left first.
``<-'`
  Sequential with instruction on the right first.
``||'`
  Parallel

The D10V syntax allows either one instruction per line, one instruction per line with the execution symbol, or two instructions per line. For example

`abs a1 -> abs r0`
  Execute these sequentially. The instruction on the right is in the right container and is executed second.
`abs r0 <- abs a1`
  Execute these reverse-sequentially. The instruction on the right is in the right container, and is executed first.
`ld2w r2,@r8+ || mac a0,r0,r7`
  Execute these in parallel.
`ld2w r2,@r8+ ||`
`mac a0,r0,r7`
  Two-line format. Execute these in parallel.
`ld2w r2,@r8+`
`mac a0,r0,r7`
  Two-line format. Execute these sequentially. Assembler will put them in the proper containers.
`ld2w r2,@r8+ ->`
`mac a0,r0,r7`
  Two-line format. Execute these sequentially. Same as above but second instruction will always go into right container.

Since ``$'` has no special meaning, you may use it in symbol names.

#### 8.4.2.4 Register Names

You can use the predefined symbols ``r0'` through ``r15'` to refer to the D10V registers. You can also use ``sp'` as an alias for ``r15'`. The accumulators are ``a0'` and ``a1'`. There are special register-pair names that may optionally be used in opcodes that require even-numbered registers. Register names are not case sensitive.

Register Pairs

`r0-r1`
`r2-r3`
`r4-r5`
`r6-r7`
`r8-r9`
`r10-r11`
`r12-r13`
`r14-r15`

The D10V also has predefined symbols for these control registers and status bits:

`psw`
  Processor Status Word
`bpsw`
  Backup Processor Status Word
`pc`
  Program Counter
`bpc`
  Backup Program Counter
`rpt_c`
  Repeat Count
`rpt_s`
  Repeat Start address
`rpt_e`
  Repeat End address
`mod_s`
  Modulo Start address
`mod_e`
  Modulo End address
`iba`
  Instruction Break Address
`f0`
  Flag 0
`f1`
  Flag 1
`c`
  Carry flag

#### 8.4.2.5 Addressing Modes

`as` understands the following addressing modes for the D10V. `Rn` in the following refers to any of the numbered registers, but not the control registers.

`Rn`
  Register direct
`@Rn`
  Register indirect
`@Rn+`
  Register indirect with post-increment
`@Rn-`
  Register indirect with post-decrement
`@-SP`
  Register indirect with pre-decrement
`@(disp, Rn)`
  Register indirect with displacement
`addr`
  PC relative address (for branch or rep).
`#imm`
  Immediate data (the ``#'` is optional and ignored)

#### 8.4.2.6 @WORD Modifier

Any symbol followed by `@word` will be replaced by the symbol's value shifted right by 2. This is used in situations such as loading a register with the address of a function (or any other code fragment). For example, if you want to load a register with the location of the function `main` then jump to that function, you could do it as follws:

    ldi     r2, main@word
    jmp     r2

### 8.4.3 Floating Point

The D10V has no hardware floating point, but the `.float` and `.double` directives generates IEEE floating-point numbers for compatibility with other development tools.

### 8.4.4 Opcodes

For detailed information on the D10V machine instruction set, see D10V Architecture: A VLIW Microprocessor for Multimedia Applications (Mitsubishi Electric Corp.). `as` implements all the standard D10V opcodes. The only changes are those described in the section on size modifiers

## 8.5 D30V Dependent Features

### 8.5.1 D30V Options

The Mitsubishi D30V version of `as` has a few machine dependent options.

``-O'`
  The D30V can often execute two sub-instructions in parallel. When this option is used, `as` will attempt to optimize its output by detecting when instructions can be executed in parallel.
``-n'`
  When this option is used, `as` will issue a warning every time it adds a nop instruction.
``-N'`
  When this option is used, `as` will issue a warning if it needs to insert a nop after a 32-bit multiply before a load or 16-bit multiply instruction.

### 8.5.2 Syntax

The D30V syntax is based on the syntax in Mitsubishi's D30V architecture manual. The differences are detailed below.

#### 8.5.2.1 Size Modifiers

The D30V version of `as` uses the instruction names in the D30V Architecture Manual. However, the names in the manual are sometimes ambiguous. There are instruction names that can assemble to a short or long form opcode. How does the assembler pick the correct form? `as` will always pick the smallest form if it can. When dealing with a symbol that is not defined yet when a line is being assembled, it will always use the long form. If you need to force the assembler to use either the short or long form of the instruction, you can append either ``.s'` (short) or ``.l'` (long) to it. For example, if you are writing an assembly program and you want to do a branch to a symbol that is defined later in your program, you can write ``bra.s foo'`. Objdump and GDB will always append ``.s'` or ``.l'` to instructions which have both short and long forms.

#### 8.5.2.2 Sub-Instructions

The D30V assembler takes as input a series of instructions, either one-per-line, or in the special two-per-line format described in the next section. Some of these instructions will be short-form or sub-instructions. These sub-instructions can be packed into a single instruction. The assembler will do this automatically. It will also detect when it should not pack instructions. For example, when a label is defined, the next instruction will never be packaged with the previous one. Whenever a branch and link instruction is called, it will not be packaged with the next instruction so the return address will be valid. Nops are automatically inserted when necessary.

If you do not want the assembler automatically making these decisions, you can control the packaging and execution type (parallel or sequential) with the special execution symbols described in the next section.

#### 8.5.2.3 Special Characters

``;'` and ``#'` are the line comment characters. Sub-instructions may be executed in order, in reverse-order, or in parallel. Instructions listed in the standard one-per-line format will be executed sequentially unless you use the ``-O'` option.

To specify the executing order, use the following symbols:

``->'`
  Sequential with instruction on the left first.
``<-'`
  Sequential with instruction on the right first.
``||'`
  Parallel

The D30V syntax allows either one instruction per line, one instruction per line with the execution symbol, or two instructions per line. For example

`abs r2,r3 -> abs r4,r5`
  Execute these sequentially. The instruction on the right is in the right container and is executed second.
`abs r2,r3 <- abs r4,r5`
  Execute these reverse-sequentially. The instruction on the right is in the right container, and is executed first.
`abs r2,r3 || abs r4,r5`
  Execute these in parallel.
`ldw r2,@(r3,r4) ||`
`mulx r6,r8,r9`
  Two-line format. Execute these in parallel.
`mulx a0,r8,r9`
`stw r2,@(r3,r4)`
  Two-line format. Execute these sequentially unless ``-O'` option is used. If the ``-O'` option is used, the assembler will determine if the instructions could be done in parallel (the above two instructions can be done in parallel), and if so, emit them as parallel instructions. The assembler will put them in the proper containers. In the above example, the assembler will put the ``stw'` instruction in left container and the ``mulx'` instruction in the right container.
`stw r2,@(r3,r4) ->`
`mulx a0,r8,r9`
  Two-line format. Execute the ``stw'` instruction followed by the ``mulx'` instruction sequentially. The first instruction goes in the left container and the second instruction goes into right container. The assembler will give an error if the machine ordering constraints are violated.
`stw r2,@(r3,r4) <-`
`mulx a0,r8,r9`
  Same as previous example, except that the ``mulx'` instruction is executed before the ``stw'` instruction.

Since ``$'` has no special meaning, you may use it in symbol names.

#### 8.5.2.4 Guarded Execution

`as` supports the full range of guarded execution directives for each instruction. Just append the directive after the instruction proper. The directives are:

``/tx'`
  Execute the instruction if flag f0 is true.
``/fx'`
  Execute the instruction if flag f0 is false.
``/xt'`
  Execute the instruction if flag f1 is true.
``/xf'`
  Execute the instruction if flag f1 is false.
``/tt'`
  Execute the instruction if both flags f0 and f1 are true.
``/tf'`
  Execute the instruction if flag f0 is true and flag f1 is false.

#### 8.5.2.5 Register Names

You can use the predefined symbols ``r0'` through ``r63'` to refer to the D30V registers. You can also use ``sp'` as an alias for ``r63'` and ``link'` as an alias for ``r62'`. The accumulators are ``a0'` and ``a1'`.

The D30V also has predefined symbols for these control registers and status bits:

`psw`
  Processor Status Word
`bpsw`
  Backup Processor Status Word
`pc`
  Program Counter
`bpc`
  Backup Program Counter
`rpt_c`
  Repeat Count
`rpt_s`
  Repeat Start address
`rpt_e`
  Repeat End address
`mod_s`
  Modulo Start address
`mod_e`
  Modulo End address
`iba`
  Instruction Break Address
`f0`
  Flag 0
`f1`
  Flag 1
`f2`
  Flag 2
`f3`
  Flag 3
`f4`
  Flag 4
`f5`
  Flag 5
`f6`
  Flag 6
`f7`
  Flag 7
`s`
  Same as flag 4 (saturation flag)
`v`
  Same as flag 5 (overflow flag)
`va`
  Same as flag 6 (sticky overflow flag)
`c`
  Same as flag 7 (carry/borrow flag)
`b`
  Same as flag 7 (carry/borrow flag)

#### 8.5.2.6 Addressing Modes

`as` understands the following addressing modes for the D30V. `Rn` in the following refers to any of the numbered registers, but not the control registers.

`Rn`
  Register direct
`@Rn`
  Register indirect
`@Rn+`
  Register indirect with post-increment
`@Rn-`
  Register indirect with post-decrement
`@-SP`
  Register indirect with pre-decrement
`@(disp, Rn)`
  Register indirect with displacement
`addr`
  PC relative address (for branch or rep).
`#imm`
  Immediate data (the ``#'` is optional and ignored)

### 8.5.3 Floating Point

The D30V has no hardware floating point, but the `.float` and `.double` directives generates IEEE floating-point numbers for compatibility with other development tools.

### 8.5.4 Opcodes

For detailed information on the D30V machine instruction set, see D30V Architecture: A VLIW Microprocessor for Multimedia Applications (Mitsubishi Electric Corp.). `as` implements all the standard D30V opcodes. The only changes are those described in the section on size modifiers

## 8.6 H8/300 Dependent Features

### 8.6.1 Options

`as` has no additional command-line options for the Hitachi H8/300 family.

### 8.6.2 Syntax

#### 8.6.2.1 Special Characters

``;'` is the line comment character.

``$'` can be used instead of a newline to separate statements. Therefore you may not use ``$'` in symbol names on the H8/300.

#### 8.6.2.2 Register Names

You can use predefined symbols of the form ``rnh'` and ``rnl'` to refer to the H8/300 registers as sixteen 8-bit general-purpose registers. n is a digit from ``0'` to ``7'`); for instance, both ``r0h'` and ``r7l'` are valid register names.

You can also use the eight predefined symbols ``rn'` to refer to the H8/300 registers as 16-bit registers (you must use this form for addressing).

On the H8/300H, you can also use the eight predefined symbols ``ern'` (``er0'` ... ``er7'`) to refer to the 32-bit general purpose registers.

The two control registers are called `pc` (program counter; a 16-bit register, except on the H8/300H where it is 24 bits) and `ccr` (condition code register; an 8-bit register). `r7` is used as the stack pointer, and can also be called `sp`.

#### 8.6.2.3 Addressing Modes

as understands the following addressing modes for the H8/300:

`rn`
  Register direct
`@rn`
  Register indirect
`@(d, rn)`
`@(d:16, rn)`
`@(d:24, rn)`
  Register indirect: 16-bit or 24-bit displacement d from register n. (24-bit displacements are only meaningful on the H8/300H.)
`@rn+`
  Register indirect with post-increment
`@-rn`
  Register indirect with pre-decrement
``@`aa`
``@`aa:8`
``@`aa:16`
``@`aa:24`
  Absolute address `aa`. (The address size ``:24'` only makes sense on the H8/300H.)
`#xx`
`#xx:8`
`#xx:16`
`#xx:32`
  Immediate data xx. You may specify the ``:8'`, ``:16'`, or ``:32'` for clarity, if you wish; but `as` neither requires this nor uses it--the data size required is taken from context.
``@``@`aa`
``@``@`aa:8`
  Memory indirect. You may specify the ``:8'` for clarity, if you wish; but `as` neither requires this nor uses it.

### 8.6.3 Floating Point

The H8/300 family has no hardware floating point, but the `.float` directive generates IEEE floating-point numbers for compatibility with other development tools.

### 8.6.4 H8/300 Machine Directives

`as` has only one machine-dependent directive for the H8/300:

`.h8300h`
  Recognize and emit additional instructions for the H8/300H variant, and also make `.int` emit 32-bit numbers rather than the usual (16-bit) for the H8/300 family.

On the H8/300 family (including the H8/300H) ``.word'` directives generate 16-bit numbers.

### 8.6.5 Opcodes

For detailed information on the H8/300 machine instruction set, see H8/300 Series Programming Manual (Hitachi ADE--602--025). For information specific to the H8/300H, see H8/300H Series Programming Manual (Hitachi).

`as` implements all the standard H8/300 opcodes. No additional pseudo-instructions are needed on this family.

Four H8/300 instructions (`add`, `cmp`, `mov`, `sub`) are defined with variants using the suffixes ``.b'`, ``.w'`, and ``.l'` to specify the size of a memory operand. `as` supports these suffixes, but does not require them; since one of the operands is always a register, `as` can deduce the correct size.

For example, since `r0` refers to a 16-bit register,

    mov    r0,@foo
    is equivalent to
    mov.w  r0,@foo

If you use the size suffixes, `as` issues a warning when the suffix and the register size do not match.

## 8.7 H8/500 Dependent Features

### 8.7.1 Options

`as` has no additional command-line options for the Hitachi H8/500 family.

### 8.7.2 Syntax

#### 8.7.2.1 Special Characters

``!'` is the line comment character.

``;'` can be used instead of a newline to separate statements.

Since ``$'` has no special meaning, you may use it in symbol names.

#### 8.7.2.2 Register Names

You can use the predefined symbols ``r0'`, ``r1'`, ``r2'`, ``r3'`, ``r4'`, ``r5'`, ``r6'`, and ``r7'` to refer to the H8/500 registers.

The H8/500 also has these control registers:

`cp`
  code pointer
`dp`
  data pointer
`bp`
  base pointer
`tp`
  stack top pointer
`ep`
  extra pointer
`sr`
  status register
`ccr`
  condition code register

All registers are 16 bits long. To represent 32 bit numbers, use two adjacent registers; for distant memory addresses, use one of the segment pointers (`cp` for the program counter; `dp` for `r0`--`r3`; `ep` for `r4` and `r5`; and `tp` for `r6` and `r7`.

#### 8.7.2.3 Addressing Modes

as understands the following addressing modes for the H8/500:

`Rn`
  Register direct
`@Rn`
  Register indirect
`@(d:8, Rn)`
  Register indirect with 8 bit signed displacement
`@(d:16, Rn)`
  Register indirect with 16 bit signed displacement
`@-Rn`
  Register indirect with pre-decrement
`@Rn+`
  Register indirect with post-increment
`@aa:8`
  8 bit absolute address
`@aa:16`
  16 bit absolute address
`#xx:8`
  8 bit immediate
`#xx:16`
  16 bit immediate

### 8.7.3 Floating Point

The H8/500 family has no hardware floating point, but the `.float` directive generates IEEE floating-point numbers for compatibility with other development tools.

### 8.7.4 H8/500 Machine Directives

`as` has no machine-dependent directives for the H8/500. However, on this platform the ``.int'` and ``.word'` directives generate 16-bit numbers.

### 8.7.5 Opcodes

For detailed information on the H8/500 machine instruction set, see H8/500 Series Programming Manual (Hitachi M21T001).

`as` implements all the standard H8/500 opcodes. No additional pseudo-instructions are needed on this family.

## 8.8 HPPA Dependent Features

### 8.8.1 Notes

As a back end for GNU CC `as` has been throughly tested and should work extremely well. We have tested it only minimally on hand written assembly code and no one has tested it much on the assembly output from the HP compilers.

The format of the debugging sections has changed since the original `as` port (version 1.3X) was released; therefore, you must rebuild all HPPA objects and libraries with the new assembler so that you can debug the final executable.

The HPPA `as` port generates a small subset of the relocations available in the SOM and ELF object file formats. Additional relocation support will be added as it becomes necessary.

### 8.8.2 Options

`as` has no machine-dependent command-line options for the HPPA.

### 8.8.3 Syntax

The assembler syntax closely follows the HPPA instruction set reference manual; assembler directives and general syntax closely follow the HPPA assembly language reference manual, with a few noteworthy differences.

First, a colon may immediately follow a label definition. This is simply for compatibility with how most assembly language programmers write code.

Some obscure expression parsing problems may affect hand written code which uses the `spop` instructions, or code which makes significant use of the `!` line separator.

`as` is much less forgiving about missing arguments and other similar oversights than the HP assembler. `as` notifies you of missing arguments as syntax errors; this is regarded as a feature, not a bug.

Finally, `as` allows you to use an external symbol without explicitly importing the symbol. Warning: in the future this will be an error for HPPA targets.

Special characters for HPPA targets include:

``;'` is the line comment character.

``!'` can be used instead of a newline to separate statements.

Since ``$'` has no special meaning, you may use it in symbol names.

### 8.8.4 Floating Point

The HPPA family uses IEEE floating-point numbers.

### 8.8.5 HPPA Assembler Directives

`as` for the HPPA supports many additional directives for compatibility with the native assembler. This section describes them only briefly. For detailed information on HPPA-specific assembler directives, see HP9000 Series 800 Assembly Language Reference Manual (HP 92432-90001).

`as` does not support the following assembler directives described in the HP manual:

    .endm           .liston
    .enter          .locct
    .leave          .macro
    .listoff

Beyond those implemented for compatibility, `as` supports one additional assembler directive for the HPPA: `.param`. It conveys register argument locations for static functions. Its syntax closely follows the `.export` directive.

These are the additional directives in `as` for the HPPA:

`.block n`
`.blockz n`
  Reserve n bytes of storage, and initialize them to zero.
`.call`
  Mark the beginning of a procedure call. Only the special case with no arguments is allowed.
`.callinfo [ param=value, ... ] [ flag, ... ]`
  Specify a number of parameters and flags that define the environment for a procedure. param may be any of ``frame'` (frame size), ``entry_gr'` (end of general register range), ``entry_fr'` (end of float register range), ``entry_sr'` (end of space register range). The values for flag are ``calls'` or ``caller'` (proc has subroutines), ``no_calls'` (proc does not call subroutines), ``save_rp'` (preserve return pointer), ``save_sp'` (proc preserves stack pointer), ``no_unwind'` (do not unwind this proc), ``hpux_int'` (proc is interrupt routine).
`.code`
  Assemble into the standard section called ``$TEXT$'`, subsection ``$CODE$'`.
`.copyright "string"`
  In the SOM object format, insert string into the object code, marked as a copyright string.
`.copyright "string"`
  In the ELF object format, insert string into the object code, marked as a version string.
`.enter`
  Not yet supported; the assembler rejects programs containing this directive.
`.entry`
  Mark the beginning of a procedure.
`.exit`
  Mark the end of a procedure.
`.export name [ ,typ ] [ ,param=r ]`
  Make a procedure name available to callers. typ, if present, must be one of ``absolute'`, ``code'` (ELF only, not SOM), ``data'`, ``entry'`, ``data'`, ``entry'`, ``millicode'`, ``plabel'`, ``pri_prog'`, or ``sec_prog'`. param, if present, provides either relocation information for the procedure arguments and result, or a privilege level. param may be ``argwn'` (where n ranges from `0` to `3`, and indicates one of four one-word arguments); ``rtnval'` (the procedure's result); or ``priv_lev'` (privilege level). For arguments or the result, r specifies how to relocate, and must be one of ``no'` (not relocatable), ``gr'` (argument is in general register), ``fr'` (in floating point register), or ``fu'` (upper half of float register). For ``priv_lev'`, r is an integer.
`.half n`
  Define a two-byte integer constant n; synonym for the portable `as` directive `.short`.
`.import name [ ,typ ]`
  Converse of `.export`; make a procedure available to call. The arguments use the same conventions as the first two arguments for `.export`.
`.label name`
  Define name as a label for the current assembly location.
`.leave`
  Not yet supported; the assembler rejects programs containing this directive.
`.origin lc`
  Advance location counter to lc. Synonym for the `` portable directive `.org`.
`.param name [ ,typ ] [ ,param=r ]`
  Similar to `.export`, but used for static procedures.
`.proc`
  Use preceding the first statement of a procedure.
`.procend`
  Use following the last statement of a procedure.
`label .reg expr`
  Synonym for `.equ`; define label with the absolute expression expr as its value.
`.space secname [ ,params ]`
  Switch to section secname, creating a new section by that name if necessary. You may only use params when creating a new section, not when switching to an existing one. secname may identify a section by number rather than by name. If specified, the list params declares attributes of the section, identified by keywords. The keywords recognized are ``spnum=exp'` (identify this section by the number exp, an absolute expression), ``sort=exp'` (order sections according to this sort key when linking; exp is an absolute expression), ``unloadable'` (section contains no loadable data), ``notdefined'` (this section defined elsewhere), and ``private'` (data in this section not available to other programs).
`.spnum secnam`
  Allocate four bytes of storage, and initialize them with the section number of the section named secnam. (You can define the section number with the HPPA `.space` directive.)
`.string "str"`
  Copy the characters in the string str to the object file. See section 3.6.1.1 Strings, for information on escape sequences you can use in `as` strings. Warning! The HPPA version of `.string` differs from the usual `as` definition: it does not write a zero byte after copying str.
`.stringz "str"`
  Like `.string`, but appends a zero byte after copying str to object file.
`.subspa name [ ,params ]`
`.nsubspa name [ ,params ]`
  Similar to `.space`, but selects a subsection name within the current section. You may only specify params when you create a subsection (in the first instance of `.subspa` for this name). If specified, the list params declares attributes of the subsection, identified by keywords. The keywords recognized are ``quad=expr'` ("quadrant" for this subsection), ``align=expr'` (alignment for beginning of this subsection; a power of two), ``access=expr'` (value for "access rights" field), ``sort=expr'` (sorting order for this subspace in link), ``code_only'` (subsection contains only code), ``unloadable'` (subsection cannot be loaded into memory), ``common'` (subsection is common block), ``dup_comm'` (initialized data may have duplicate names), or ``zero'` (subsection is all zeros, do not write in object file). `.nsubspa` always creates a new subspace with the given name, even if one with the same name already exists.
`.version "str"`
  Write str as version identifier in object code.

### 8.8.6 Opcodes

For detailed information on the HPPA machine instruction set, see PA-RISC Architecture and Instruction Set Reference Manual (HP 09740-90039).

## 8.9 80386 Dependent Features

### 8.9.1 Options

The 80386 has no machine dependent options.

### 8.9.2 AT&T Syntax versus Intel Syntax

In order to maintain compatibility with the output of `gcc`, `as` supports AT&T System V/386 assembler syntax. This is quite different from Intel syntax. We mention these differences because almost all 80386 documents use Intel syntax. Notable differences between the two syntaxes are:

- AT&T immediate operands are preceded by ``$'`; Intel immediate operands are undelimited (Intel ``push 4'` is AT&T ``pushl $4'`). AT&T register operands are preceded by ``%'`; Intel register operands are undelimited. AT&T absolute (as opposed to PC relative) jump/call operands are prefixed by ``*'`; they are undelimited in Intel syntax.
- AT&T and Intel syntax use the opposite order for source and destination operands. Intel ``add eax, 4'` is ``addl $4, %eax'`. The ``source, dest'` convention is maintained for compatibility with previous Unix assemblers. Note that instructions with more than one source operand, such as the ``enter'` instruction, do not have reversed order. section 8.9.11 AT&T Syntax bugs.
- In AT&T syntax the size of memory operands is determined from the last character of the instruction mnemonic. Mnemonic suffixes of ``b'`, ``w'`, and ``l'` specify byte (8-bit), word (16-bit), and long (32-bit) memory references. Intel syntax accomplishes this by prefixing memory operands (not the instruction mnemonics) with ``byte ptr'`, ``word ptr'`, and ``dword ptr'`. Thus, Intel ``mov al, byte ptr foo'` is ``movb foo, %al'` in AT&T syntax.
- Immediate form long jumps and calls are ``lcall/ljmp $section, $offset'` in AT&T syntax; the Intel syntax is ``call/jmp far section:offset'`. Also, the far return instruction is ``lret $stack-adjust'` in AT&T syntax; Intel syntax is ``ret far stack-adjust'`.
- The AT&T assembler does not provide support for multiple section programs. Unix style systems expect all programs to be single sections.

### 8.9.3 Instruction Naming

Instruction mnemonics are suffixed with one character modifiers which specify the size of operands. The letters ``b'`, ``w'`, and ``l'` specify byte, word, and long operands. If no suffix is specified by an instruction then `as` tries to fill in the missing suffix based on the destination register operand (the last one by convention). Thus, ``mov %ax, %bx'` is equivalent to ``movw %ax, %bx'`; also, ``mov $1, %bx'` is equivalent to ``movw $1, %bx'`. Note that this is incompatible with the AT&T Unix assembler which assumes that a missing mnemonic suffix implies long operand size. (This incompatibility does not affect compiler output since compilers always explicitly specify the mnemonic suffix.)

Almost all instructions have the same names in AT&T and Intel format. There are a few exceptions. The sign extend and zero extend instructions need two sizes to specify them. They need a size to sign/zero extend from and a size to zero extend to. This is accomplished by using two instruction mnemonic suffixes in AT&T syntax. Base names for sign extend and zero extend are ``movs...'` and ``movz...'` in AT&T syntax (``movsx'` and ``movzx'` in Intel syntax). The instruction mnemonic suffixes are tacked on to this base name, the from suffix before the to suffix. Thus, ``movsbl %al, %edx'` is AT&T syntax for "move sign extend from %al to %edx." Possible suffixes, thus, are ``bl'` (from byte to long), ``bw'` (from byte to word), and ``wl'` (from word to long).

The Intel-syntax conversion instructions

- ``cbw'` -- sign-extend byte in ``%al'` to word in ``%ax'`,
- ``cwde'` -- sign-extend word in ``%ax'` to long in ``%eax'`,
- ``cwd'` -- sign-extend word in ``%ax'` to long in ``%dx:%ax'`,
- ``cdq'` -- sign-extend dword in ``%eax'` to quad in ``%edx:%eax'`,

are called ``cbtw'`, ``cwtl'`, ``cwtd'`, and ``cltd'` in AT&T naming. `as` accepts either naming for these instructions.

Far call/jump instructions are ``lcall'` and ``ljmp'` in AT&T syntax, but are ``call far'` and ``jump far'` in Intel convention.

### 8.9.4 Register Naming

Register operands are always prefixed with ``%'`. The 80386 registers consist of

- the 8 32-bit registers ``%eax'` (the accumulator), ``%ebx'`, ``%ecx'`, ``%edx'`, ``%edi'`, ``%esi'`, ``%ebp'` (the frame pointer), and ``%esp'` (the stack pointer).
- the 8 16-bit low-ends of these: ``%ax'`, ``%bx'`, ``%cx'`, ``%dx'`, ``%di'`, ``%si'`, ``%bp'`, and ``%sp'`.
- the 8 8-bit registers: ``%ah'`, ``%al'`, ``%bh'`, ``%bl'`, ``%ch'`, ``%cl'`, ``%dh'`, and ``%dl'` (These are the high-bytes and low-bytes of ``%ax'`, ``%bx'`, ``%cx'`, and ``%dx'`)
- the 6 section registers ``%cs'` (code section), ``%ds'` (data section), ``%ss'` (stack section), ``%es'`, ``%fs'`, and ``%gs'`.
- the 3 processor control registers ``%cr0'`, ``%cr2'`, and ``%cr3'`.
- the 6 debug registers ``%db0'`, ``%db1'`, ``%db2'`, ``%db3'`, ``%db6'`, and ``%db7'`.
- the 2 test registers ``%tr6'` and ``%tr7'`.
- the 8 floating point register stack ``%st'` or equivalently ``%st(0)'`, ``%st(1)'`, ``%st(2)'`, ``%st(3)'`, ``%st(4)'`, ``%st(5)'`, ``%st(6)'`, and ``%st(7)'`.

### 8.9.5 Instruction Prefixes

Instruction prefixes are used to modify the following instruction. They are used to repeat string instructions, to provide section overrides, to perform bus lock operations, and to change operand and address sizes. (Most instructions that normally operate on 32-bit operands will use 16-bit operands if the instruction has an "operand size" prefix.) Instruction prefixes are best written on the same line as the instruction they act upon. For example, the ``scas'` (scan string) instruction is repeated with:

            repne scas %es:(%edi),%al

You may also place prefixes on the lines immediately preceding the instruction, but this circumvents checks that `as` does with prefixes, and will not work with all prefixes.

Here is a list of instruction prefixes:

- Section override prefixes ``cs'`, ``ds'`, ``ss'`, ``es'`, ``fs'`, ``gs'`. These are automatically added by specifying using the section:memory-operand form for memory references.
- Operand/Address size prefixes ``data16'` and ``addr16'` change 32-bit operands/addresses into 16-bit operands/addresses, while ``data32'` and ``addr32'` change 16-bit ones (in a `.code16` section) into 32-bit operands/addresses. These prefixes must appear on the same line of code as the instruction they modify. For example, in a 16-bit `.code16` section, you might write:

              addr32 jmpl *(%ebx)

- The bus lock prefix ``lock'` inhibits interrupts during execution of the instruction it precedes. (This is only valid with certain instructions; see a 80386 manual for details).
- The wait for coprocessor prefix ``wait'` waits for the coprocessor to complete the current instruction. This should never be needed for the 80386/80387 combination.
- The ``rep'`, ``repe'`, and ``repne'` prefixes are added to string instructions to make them repeat ``%ecx'` times (``%cx'` times if the current address size is 16-bits).

### 8.9.6 Memory References

An Intel syntax indirect memory reference of the form

    section:[base + index*scale + disp]

is translated into the AT&T syntax

    section:disp(base, index, scale)

where base and index are the optional 32-bit base and index registers, disp is the optional displacement, and scale, taking the values 1, 2, 4, and 8, multiplies index to calculate the address of the operand. If no scale is specified, scale is taken to be 1. section specifies the optional section register for the memory operand, and may override the default section register (see a 80386 manual for section register defaults). Note that section overrides in AT&T syntax must be preceded by a ``%'`. If you specify a section override which coincides with the default section register, `as` does not output any section register override prefixes to assemble the given instruction. Thus, section overrides can be specified to emphasize which section register is used for a given memory operand.

Here are some examples of Intel and AT&T style memory references:

AT&T: ``-4(%ebp)'`, Intel: ``[ebp - 4]'`
  base is ``%ebp'`; disp is ``-4'`. section is missing, and the default section is used (``%ss'` for addressing with ``%ebp'` as the base register). index, scale are both missing.
AT&T: ``foo(,%eax,4)'`, Intel: ``[foo + eax*4]'`
  index is ``%eax'` (scaled by a scale 4); disp is ``foo'`. All other fields are missing. The section register here defaults to ``%ds'`.
AT&T: ``foo(,1)'`; Intel ``[foo]'`
  This uses the value pointed to by ``foo'` as a memory operand. Note that base and index are both missing, but there is only one ``,'`. This is a syntactic exception.
AT&T: ``%gs:foo'`; Intel ``gs:foo'`
  This selects the contents of the variable ``foo'` with section register section being ``%gs'`.

Absolute (as opposed to PC relative) call and jump operands must be prefixed with ``*'`. If no ``*'` is specified, `as` always chooses PC relative addressing for jump/call labels.

Any instruction that has a memory operand, but no register operand, must specify its size (byte, word, or long) with an instruction mnemonic suffix (``b'`, ``w'`, or ``l'`, respectively).

### 8.9.7 Handling of Jump Instructions

Jump instructions are always optimized to use the smallest possible displacements. This is accomplished by using byte (8-bit) displacement jumps whenever the target is sufficiently close. If a byte displacement is insufficient a long (32-bit) displacement is used. We do not support word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump instruction with the ``data16'` instruction prefix), since the 80386 insists upon masking ``%eip'` to 16 bits after the word displacement is added.

Note that the ``jcxz'`, ``jecxz'`, ``loop'`, ``loopz'`, ``loope'`, ``loopnz'` and ``loopne'` instructions only come in byte displacements, so that if you use these instructions (`gcc` does not use them) you may get an error message (and incorrect code). The AT&T 80386 assembler tries to get around this problem by expanding ``jcxz foo'` to

             jcxz cx_zero
             jmp cx_nonzero
    cx_zero: jmp foo
    cx_nonzero:

### 8.9.8 Floating Point

All 80387 floating point types except packed BCD are supported. (BCD support may be added without much difficulty). These data types are 16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), and extended (80-bit) precision floating point. Each supported type has an instruction mnemonic suffix and a constructor associated with it. Instruction mnemonic suffixes specify the operand's data type. Constructors build these data types into memory.

- Floating point constructors are ``.float'` or ``.single'`, ``.double'`, and ``.tfloat'` for 32-, 64-, and 80-bit formats. These correspond to instruction mnemonic suffixes ``s'`, ``l'`, and ``t'`. ``t'` stands for 80-bit (ten byte) real. The 80387 only supports this format via the ``fldt'` (load 80-bit real to stack top) and ``fstpt'` (store 80-bit real and pop stack) instructions.
- Integer constructors are ``.word'`, ``.long'` or ``.int'`, and ``.quad'` for the 16-, 32-, and 64-bit integer formats. The corresponding instruction mnemonic suffixes are ``s'` (single), ``l'` (long), and ``q'` (quad). As with the 80-bit real format, the 64-bit ``q'` format is only present in the ``fildq'` (load quad integer to stack top) and ``fistpq'` (store quad integer and pop stack) instructions.

Register to register operations should not use instruction mnemonic suffixes. ``fstl %st, %st(1)'` will give a warning, and be assembled as if you wrote ``fst %st, %st(1)'`, since all register to register operations use 80-bit floating point operands. (Contrast this with ``fstl %st, mem'`, which converts ``%st'` from 80-bit to 64-bit floating point format, then stores the result in the 4 byte location ``mem'`)

### 8.9.9 Intel's MMX and AMD's 3DNow! SIMD Operations

`as` supports Intel's MMX instruction set (SIMD instructions for integer data), available on Intel's Pentium MMX processors and Pentium II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow! instruction set (SIMD instructions for 32-bit floating point data) available on AMD's K6-2 processor and possibly others in the future.

Currently, `as` does not support Intel's floating point SIMD, Katmai (KNI).

The eight 64-bit MMX operands, also used by 3DNow!, are called ``%mm0'`, ``%mm1'`, ... ``%mm7'`. They contain eight 8-bit integers, four 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit floating point values. The MMX registers cannot be used at the same time as the floating point stack.

See Intel and AMD documentation, keeping in mind that the operand order in instructions is reversed from the Intel syntax.

### 8.9.10 Writing 16-bit Code

While `as` normally writes only "pure" 32-bit i386 code, it also supports writing code to run in real mode or in 16-bit protected mode code segments. To do this, put a ``.code16'` directive before the assembly language instructions to be run in 16-bit mode. You can switch `as` back to writing normal 32-bit code with the ``.code32'` directive.

The code which `as` generates in 16-bit mode will not necessarily run on a 16-bit pre-80386 processor. To write code that runs on such a processor, you must refrain from using any 32-bit constructs which require `as` to output address or operand size prefixes.

Note that writing 16-bit code instructions by explicitly specifying a prefix or an instruction mnemonic suffix within a 32-bit code section generates different machine instructions than those generated for a 16-bit code segment. In a 32-bit code section, the following code generates the machine opcode bytes ``66 6a 04'`, which pushes the value ``4'` onto the stack, decrementing ``%esp'` by 2.

            pushw $4

The same code in a 16-bit code section would generate the machine opcode bytes ``6a 04'` (ie. without the operand size prefix), which is correct since the processor default operand size is assumed to be 16 bits in a 16-bit code section.

### 8.9.11 AT&T Syntax bugs

The UnixWare assembler, and probably other AT&T derived ix86 Unix assemblers, generate floating point instructions with reversed source and destination registers in certain cases. Unfortunately, gcc and possibly many other programs use this reversed syntax, so we're stuck with it.

For example

            fsub %st,%st(3)

results in ``%st(3)'` being updated to ``%st - %st(3)'` rather than the expected ``%st(3) - %st'`. This happens with all the non-commutative arithmetic floating point operations with two register operands where the source register is ``%st'` and the destination register is ``%st(i)'`.

### 8.9.12 Notes

There is some trickery concerning the ``mul'` and ``imul'` instructions that deserves mention. The 16-, 32-, and 64-bit expanding multiplies (base opcode ``0xf6'`; extension 4 for ``mul'` and 5 for ``imul'`) can be output only in the one operand form. Thus, ``imul %ebx, %eax'` does not select the expanding multiply; the expanding multiply would clobber the ``%edx'` register, and this would confuse `gcc` output. Use ``imul %ebx'` to get the 64-bit product in ``%edx:%eax'`.

We have added a two operand form of ``imul'` when the first operand is an immediate mode expression and the second operand is a register. This is just a shorthand, so that, multiplying ``%eax'` by 69, for example, can be done with ``imul $69, %eax'` rather than ``imul $69, %eax, %eax'`.

## 8.10 Intel 80960 Dependent Features

### 8.10.1 i960 Command-line Options

`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC`
  Select the 80960 architecture. Instructions or features not supported by the selected architecture cause fatal errors. ``-ACA'` is equivalent to ``-ACA_A'`; ``-AKC'` is equivalent to ``-AMC'`. Synonyms are provided for compatibility with other tools. If you do not specify any of these options, `as` generates code for any instruction or feature that is supported by some version of the 960 (even if this means mixing architectures!). In principle, `as` attempts to deduce the minimal sufficient processor type if none is specified; depending on the object code format, the processor type may be recorded in the object file. If it is critical that the `as` output match a specific architecture, specify that architecture explicitly.
`-b`
  Add code to collect information about conditional branches taken, for later optimization using branch prediction bits. (The conditional branch instructions have branch prediction bits in the CA, CB, and CC architectures.) If BR represents a conditional branch instruction, the following represents the code generated by the assembler when ``-b'` is specified:

              call    increment routine
              .word   0       # pre-counter
      Label:  BR
              call    increment routine
              .word   0       # post-counter

  The counter following a branch records the number of times that branch was not taken; the differenc between the two counters is the number of times the branch was taken. A table of every such `Label` is also generated, so that the external postprocessor `gbr960` (supplied by Intel) can locate all the counters. This table is always labelled ``__BRANCH_TABLE__'`; this is a local symbol to permit collecting statistics for many separate object files. The table is word aligned, and begins with a two-word header. The first word, initialized to 0, is used in maintaining linked lists of branch tables. The second word is a count of the number of entries in the table, which follow immediately: each is a word, pointing to one of the labels illustrated above. The first word of the header is used to locate multiple branch tables, since each object file may contain one. Normally the links are maintained with a call to an initialization routine, placed at the beginning of each function in the file. The GNU C compiler generates these calls automatically when you give it a ``-b'` option. For further details, see the documentation of ``gbr960'`.
`-no-relax`
  Normally, Compare-and-Branch instructions with targets that require displacements greater than 13 bits (or that have external targets) are replaced with the corresponding compare (or ``chkbit'`) and branch instructions. You can use the ``-no-relax'` option to specify that `as` should generate errors instead, if the target displacement is larger than 13 bits. This option does not affect the Compare-and-Jump instructions; the code emitted for them is always adjusted when necessary (depending on displacement size), regardless of whether you use ``-no-relax'`.

### 8.10.2 Floating Point

`as` generates IEEE floating-point numbers for the directives ``.float'`, ``.double'`, ``.extended'`, and ``.single'`.

### 8.10.3 i960 Machine Directives

`.bss symbol, length, align`
  Reserve length bytes in the bss section for a local symbol, aligned to the power of two specified by align. length and align must be positive absolute expressions. This directive differs from ``.lcomm'` only in that it permits you to specify an alignment. See section 7.38 `.lcomm symbol` , length.

`.extended flonums`
  `.extended` expects zero or more flonums, separated by commas; for each flonum, ``.extended'` emits an IEEE extended-format (80-bit) floating-point number.
`.leafproc call-lab, bal-lab`
  You can use the ``.leafproc'` directive in conjunction with the optimized `callj` instruction to enable faster calls of leaf procedures. If a procedure is known to call no other procedures, you may define an entry point that skips procedure prolog code (and that does not depend on system-supplied saved context), and declare it as the bal-lab using ``.leafproc'`. If the procedure also has an entry point that goes through the normal prolog, you can specify that entry point as call-lab. A ``.leafproc'` declaration is meant for use in conjunction with the optimized call instruction ``callj'`; the directive records the data needed later to choose between converting the ``callj'` into a `bal` or a `call`. call-lab is optional; if only one argument is present, or if the two arguments are identical, the single argument is assumed to be the `bal` entry point.
`.sysproc name, index`
  The ``.sysproc'` directive defines a name for a system procedure. After you define it using ``.sysproc'`, you can use name to refer to the system procedure identified by index when calling procedures with the optimized call instruction ``callj'`. Both arguments are required; index must be between 0 and 31 (inclusive).

### 8.10.4 i960 Opcodes

All Intel 960 machine instructions are supported; see section 8.10.1 i960 Command-line Options for a discussion of selecting the instruction subset for a particular 960 architecture.

Some opcodes are processed beyond simply emitting a single corresponding instruction: ``callj'`, and Compare-and-Branch or Compare-and-Jump instructions with target displacements larger than 13 bits.

#### 8.10.4.1 `callj`

You can write `callj` to have the assembler or the linker determine the most appropriate form of subroutine call: ``call'`, ``bal'`, or ``calls'`. If the assembly source contains enough information--a ``.leafproc'` or ``.sysproc'` directive defining the operand--then `as` translates the `callj`; if not, it simply emits the `callj`, leaving it for the linker to resolve.

#### 8.10.4.2 Compare-and-Branch

The 960 architectures provide combined Compare-and-Branch instructions that permit you to store the branch target in the lower 13 bits of the instruction word itself. However, if you specify a branch target far enough away that its address won't fit in 13 bits, the assembler can either issue an error, or convert your Compare-and-Branch instruction into separate instructions to do the compare and the branch.

Whether `as` gives an error or expands the instruction depends on two choices you can make: whether you use the ``-no-relax'` option, and whether you use a "Compare and Branch" instruction or a "Compare and Jump" instruction. The "Jump" instructions are always expanded if necessary; the "Branch" instructions are expanded when necessary unless you specify `-no-relax`---in which case `as` gives an error instead.

These are the Compare-and-Branch instructions, their "Jump" variants, and the instruction pairs they may expand into:

## 8.11 M32R Dependent Features

### 8.11.1 M32R Options

The Mitsubishi M32R version of `as` has a few machine dependent options:

`-m32rx`
  `as` can assemble code for several different members of the Mitsubishi M32R family. Normally the default is to assemble code for the M32R microprocessor. This option may be used to change the default to the M32RX microprocessor, which adds some more instructions to the basic M32R instruction set, and some additional parameters to some of the original instructions.
`-warn-explicit-parallel-conflicts`
  Instructs `as` to produce warning messages when questionable parallel instructions are encountered. This option is enabled by default, but `gcc` disables it when it invokes `as` directly. Questionable instructions are those whoes behaviour would be different if they were executed sequentially. For example the code fragment ``mv r1, r2 || mv r3, r1'` produces a different result from ``mv r1, r2 \n mv r3, r1'` since the former moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1 and r3.
`-Wp`
  This is a shorter synonym for the -warn-explicit-parallel-conflicts option.
`-no-warn-explicit-parallel-conflicts`
  Instructs `as` not to produce warning messages when questionable parallel instructions are encountered.
`-Wnp`
  This is a shorter synonym for the -no-warn-explicit-parallel-conflicts option.

### 8.11.2 M32R Warnings

There are several warning and error messages that can be produced by `as` which are specific to the M32R:

`output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?`
  This message is only produced if warnings for explicit parallel conflicts have been enabled. It indicates that the assembler has encountered a parallel instruction in which the destination register of the left hand instruction is used as an input register in the right hand instruction. For example in this code fragment ``mv r1, r2 || neg r3, r1'` register r1 is the destination of the move instruction and the input to the neg instruction.
`output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?`
  This message is only produced if warnings for explicit parallel conflicts have been enabled. It indicates that the assembler has encountered a parallel instruction in which the destination register of the right hand instruction is used as an input register in the left hand instruction. For example in this code fragment ``mv r1, r2 || neg r2, r3'` register r2 is the destination of the neg instruction and the input to the move instruction.
`instruction ``...'` is for the M32RX only`
  This message is produced when the assembler encounters an instruction which is only supported by the M32Rx processor, and the ``-m32rx'` command line flag has not been specified to allow assembly of such instructions.
`unknown instruction ``...'``
  This message is produced when the assembler encounters an instruction which it doe snot recognise.
`only the NOP instruction can be issued in parallel on the m32r`
  This message is produced when the assembler encounters a parallel instruction which does not involve a NOP instruction and the ``-m32rx'` command line flag has not been specified. Only the M32Rx processor is able to execute two instructions in parallel.
`instruction ``...'` cannot be executed in parallel.`
  This message is produced when the assembler encounters a parallel instruction which is made up of one or two instructions which cannot be executed in parallel.
`Instructions share the same execution pipeline`
  This message is produced when the assembler encounters a parallel instruction whoes components both use the same execution pipeline.
`Instructions write to the same destination register.`
  This message is produced when the assembler encounters a parallel instruction where both components attempt to modify the same register. For example these code fragments will produce this message: ``mv r1, r2 || neg r1, r3'` ``jl r0 || mv r14, r1'` ``st r2, @-r1 || mv r1, r3'` ``mv r1, r2 || ld r0, @r1+'` ``cmp r1, r2 || addx r3, r4'` (Both write to the condition bit)

## 8.12 M680x0 Dependent Features

### 8.12.1 M680x0 Options

The Motorola 680x0 version of `as` has a few machine dependent options.

You can use the ``-l'` option to shorten the size of references to undefined symbols. If you do not use the ``-l'` option, references to undefined symbols are wide enough for a full `long` (32 bits). (Since `as` cannot know where these symbols end up, `as` can only allocate space for the linker to fill in later. Since `as` does not know how far away these symbols are, it allocates as much space as it can.) If you use this option, the references are only one word wide (16 bits). This may be useful if you want the object file to be as small as possible, and you know that the relevant symbols are always less than 17 bits away.

For some configurations, especially those where the compiler normally does not prepend an underscore to the names of user variables, the assembler requires a ``%'` before any use of a register name. This is intended to let the assembler distinguish between C variables and functions named ``a0'` through ``a7'`, and so on. The ``%'` is always accepted, but is not required for certain configurations, notably ``sun3'`. The ``--register-prefix-optional'` option may be used to permit omitting the ``%'` even for configurations for which it is normally required. If this is done, it will generally be impossible to refer to C variables and functions with the same names as register names.

Normally the character ``|'` is treated as a comment character, which means that it can not be used in expressions. The ``--bitwise-or'` option turns ``|'` into a normal character. In this mode, you must either use C style comments, or start comments with a ``#'` character at the beginning of a line.

If you use an addressing mode with a base register without specifying the size, `as` will normally use the full 32 bit value. For example, the addressing mode ``%a0@(%d0)'` is equivalent to ``%a0@(%d0:l)'`. You may use the ``--base-size-default-16'` option to tell `as` to default to using the 16 bit value. In this case, ``%a0@(%d0)'` is equivalent to ``%a0@(%d0:w)'`. You may use the ``--base-size-default-32'` option to restore the default behaviour.

If you use an addressing mode with a displacement, and the value of the displacement is not known, `as` will normally assume that the value is 32 bits. For example, if the symbol ``disp'` has not been defined, `as` will assemble the addressing mode ``%a0@(disp,%d0)'` as though ``disp'` is a 32 bit value. You may use the ``--disp-size-default-16'` option to tell `as` to instead assume that the displacement is 16 bits. In this case, `as` will assemble ``%a0@(disp,%d0)'` as though ``disp'` is a 16 bit value. You may use the ``--disp-size-default-32'` option to restore the default behaviour.

`as` can assemble code for several different members of the Motorola 680x0 family. The default depends upon how `as` was configured when it was built; normally, the default is to assemble code for the 68020 microprocessor. The following options may be used to change the default. These options control which instructions and addressing modes are permitted. The members of the 680x0 family are very similar. For detailed information about the differences, see the Motorola manuals.

``-m68000'`
``-m68ec000'`
``-m68hc000'`
``-m68hc001'`
``-m68008'`
``-m68302'`
``-m68306'`
``-m68307'`
``-m68322'`
``-m68356'`
  Assemble for the 68000. ``-m68008'`, ``-m68302'`, and so on are synonyms for ``-m68000'`, since the chips are the same from the point of view of the assembler.
``-m68010'`
  Assemble for the 68010.
``-m68020'`
``-m68ec020'`
  Assemble for the 68020. This is normally the default.
``-m68030'`
``-m68ec030'`
  Assemble for the 68030.
``-m68040'`
``-m68ec040'`
  Assemble for the 68040.
``-m68060'`
``-m68ec060'`
  Assemble for the 68060.
``-mcpu32'`
``-m68330'`
``-m68331'`
``-m68332'`
``-m68333'`
``-m68334'`
``-m68336'`
``-m68340'`
``-m68341'`
``-m68349'`
``-m68360'`
  Assemble for the CPU32 family of chips.
``-m5200'`
  Assemble for the ColdFire family of chips.
``-m68881'`
``-m68882'`
  Assemble 68881 floating point instructions. This is the default for the 68020, 68030, and the CPU32. The 68040 and 68060 always support floating point instructions.
``-mno-68881'`
  Do not assemble 68881 floating point instructions. This is the default for 68000 and the 68010. The 68040 and 68060 always support floating point instructions, even if this option is used.
``-m68851'`
  Assemble 68851 MMU instructions. This is the default for the 68020, 68030, and 68060. The 68040 accepts a somewhat different set of MMU instructions; ``-m68851'` and ``-m68040'` should not be used together.
``-mno-68851'`
  Do not assemble 68851 MMU instructions. This is the default for the 68000, 68010, and the CPU32. The 68040 accepts a somewhat different set of MMU instructions.

### 8.12.2 Syntax

This syntax for the Motorola 680x0 was developed at MIT.

The 680x0 version of `as` uses instructions names and syntax compatible with the Sun assembler. Intervening periods are ignored; for example, ``movl'` is equivalent to ``mov.l'`.

In the following table apc stands for any of the address registers (``%a0'` through ``%a7'`), the program counter (``%pc'`), the zero-address relative to the program counter (``%zpc'`), a suppressed address register (``%za0'` through ``%za7'`), or it may be omitted entirely. The use of size means one of ``w'` or ``l'`, and it may be omitted, along with the leading colon, unless a scale is also specified. The use of scale means one of ``1'`, ``2'`, ``4'`, or ``8'`, and it may always be omitted along with the leading colon.

The following addressing modes are understood:

Immediate
  ``#number'`
Data Register
  ``%d0'` through ``%d7'`
Address Register
  ``%a0'` through ``%a7'`
  ``%a7'` is also known as ``%sp'`, i.e. the Stack Pointer. `%a6` is also known as ``%fp'`, the Frame Pointer.
Address Register Indirect
  ``%a0@'` through ``%a7@'`
Address Register Postincrement
  ``%a0@+'` through ``%a7@+'`
Address Register Predecrement
  ``%a0@-'` through ``%a7@-'`
Indirect Plus Offset
  ``apc@(number)'`
Index
  ``apc@(number,register:size:scale)'` The number may be omitted.
Postindex
  ``apc@(number)@(onumber,register:size:scale)'` The onumber or the register, but not both, may be omitted.
Preindex
  ``apc@(number,register:size:scale)@(onumber)'` The number may be omitted. Omitting the register produces the Postindex addressing mode.
Absolute
  ``symbol'`, or ``digits'`, optionally followed by ``:b'`, ``:w'`, or ``:l'`.

### 8.12.3 Motorola Syntax

The standard Motorola syntax for this chip differs from the syntax already discussed (see section 8.12.2 Syntax). `as` can accept Motorola syntax for operands, even if MIT syntax is used for other operands in the same instruction. The two kinds of syntax are fully compatible.

In the following table apc stands for any of the address registers (``%a0'` through ``%a7'`), the program counter (``%pc'`), the zero-address relative to the program counter (``%zpc'`), or a suppressed address register (``%za0'` through ``%za7'`). The use of size means one of ``w'` or ``l'`, and it may always be omitted along with the leading dot. The use of scale means one of ``1'`, ``2'`, ``4'`, or ``8'`, and it may always be omitted along with the leading asterisk.

The following additional addressing modes are understood:

Address Register Indirect
  ``(%a0)'` through ``(%a7)'`
  ``%a7'` is also known as ``%sp'`, i.e. the Stack Pointer. `%a6` is also known as ``%fp'`, the Frame Pointer.
Address Register Postincrement
  ``(%a0)+'` through ``(%a7)+'`
Address Register Predecrement
  ``-(%a0)'` through ``-(%a7)'`
Indirect Plus Offset
  ``number(%a0)'` through ``number(%a7)'`, or ``number(%pc)'`. The number may also appear within the parentheses, as in ``(number,%a0)'`. When used with the pc, the number may be omitted (with an address register, omitting the number produces Address Register Indirect mode).
Index
  ``number(apc,register.size*scale)'` The number may be omitted, or it may appear within the parentheses. The apc may be omitted. The register and the apc may appear in either order. If both apc and register are address registers, and the size and scale are omitted, then the first register is taken as the base register, and the second as the index register.
Postindex
  ``([number,apc],register.size*scale,onumber)'` The onumber, or the register, or both, may be omitted. Either the number or the apc may be omitted, but not both.
Preindex
  ``([number,apc,register.size*scale],onumber)'` The number, or the apc, or the register, or any two of them, may be omitted. The onumber may be omitted. The register and the apc may appear in either order. If both apc and register are address registers, and the size and scale are omitted, then the first register is taken as the base register, and the second as the index register.

### 8.12.4 Floating Point

Packed decimal (P) format floating literals are not supported. Feel free to add the code!

The floating point formats generated by directives are these.

`.float`
  `Single` precision floating point constants.
`.double`
  `Double` precision floating point constants.
`.extend`
`.ldouble`
  `Extended` precision (`long double`) floating point constants.

### 8.12.5 680x0 Machine Directives

In order to be compatible with the Sun assembler the 680x0 assembler understands the following directives.

`.data1`
  This directive is identical to a `.data 1` directive.
`.data2`
  This directive is identical to a `.data 2` directive.
`.even`
  This directive is a special case of the `.align` directive; it aligns the output to an even byte boundary.
`.skip`
  This directive is identical to a `.space` directive.

### 8.12.6 Opcodes

#### 8.12.6.1 Branch Improvement

Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target. Generally these mnemonics are made by substituting ``j'` for ``b'` at the start of a Motorola mnemonic.

The following table summarizes the pseudo-operations. A `*` flags cases that are more fully described after the table:

              Displacement
              +-------------------------------------------------
              |                68020   68000/10
    Pseudo-Op |BYTE    WORD    LONG    LONG      non-PC relative
              +-------------------------------------------------
         jbsr |bsrs    bsr     bsrl    jsr       jsr
          jra |bras    bra     bral    jmp       jmp
    *     jXX |bXXs    bXX     bXXl    bNXs;jmpl bNXs;jmp
    *    dbXX |dbXX    dbXX        dbXX; bra; jmpl
    *    fjXX |fbXXw   fbXXw   fbXXl             fbNXw;jmp

    XX: condition
    NX: negative of condition XX

`*`---see full description below

`jbsr`
`jra`
  These are the simplest jump pseudo-operations; they always map to one particular machine instruction, depending on the displacement to the branch target.
`jXX`
  Here, ``jXX'` stands for an entire family of pseudo-operations, where XX is a conditional branch or condition-code test. The full list of pseudo-ops in this family is:

       jhi   jls   jcc   jcs   jne   jeq   jvc
       jvs   jpl   jmi   jge   jlt   jgt   jle

  For the cases of non-PC relative displacements and long displacements on the 68000 or 68010, `as` issues a longer code fragment in terms of NX, the opposite condition to XX. For example, for the non-PC relative case:

          jXX foo

  gives

           bNXs oof
           jmp foo
       oof:

`dbXX`
  The full family of pseudo-operations covered here is

       dbhi   dbls   dbcc   dbcs   dbne   dbeq   dbvc
       dbvs   dbpl   dbmi   dbge   dblt   dbgt   dble
       dbf    dbra   dbt

  Other than for word and byte displacements, when the source reads ``dbXX foo'`, `as` emits

           dbXX oo1
           bra oo2
       oo1:jmpl foo
       oo2:

`fjXX`
  This family includes

       fjne   fjeq   fjge   fjlt   fjgt   fjle   fjf
       fjt    fjgl   fjgle  fjnge  fjngl  fjngle fjngt
       fjnle  fjnlt  fjoge  fjogl  fjogt  fjole  fjolt
       fjor   fjseq  fjsf   fjsne  fjst   fjueq  fjuge
       fjugt  fjule  fjult  fjun

  For branch targets that are not PC relative, `as` emits

           fbNX oof
           jmp foo
       oof:

  when it encounters ``fjXX foo'`.

#### 8.12.6.2 Special Characters

The immediate character is ``#'` for Sun compatibility. The line-comment character is ``|'` (unless the ``--bitwise-or'` option is used). If a ``#'` appears at the beginning of a line, it is treated as a comment unless it looks like ``# line file'`, in which case it is treated normally.

## 8.13 MIPS Dependent Features

GNU `as` for MIPS architectures supports several different MIPS processors, and MIPS ISA levels I through IV. For information about the MIPS instruction set, see MIPS RISC Architecture, by Kane and Heindrich (Prentice-Hall). For an overview of MIPS assembly conventions, see "Appendix D: Assembly Language Programming" in the same work.

### 8.13.1 Assembler options

The MIPS configurations of GNU `as` support these special options:

`-G num`
  This option sets the largest size of an object that can be referenced implicitly with the `gp` register. It is only accepted for targets that use ECOFF format. The default value is 8.
`-EB`
`-EL`
  Any MIPS configuration of `as` can select big-endian or little-endian output at run time (unlike the other GNU development tools, which must be configured for one or the other). Use ``-EB'` to select big-endian output, and ``-EL'` for little-endian.
`-mips1`
`-mips2`
`-mips3`
`-mips4`
  Generate code for a particular MIPS Instruction Set Architecture level. ``-mips1'` corresponds to the R2000 and R3000 processors, ``-mips2'` to the R6000 processor, ``-mips3'` to the R4000 processor, and ``-mips4'` to the R8000 and R10000 processors. You can also switch instruction sets during the assembly; see section 8.13.4 Directives to override the ISA level.
`-mips16`
`-no-mips16`
  Generate code for the MIPS 16 processor. This is equivalent to putting ``.set mips16'` at the start of the assembly file. ``-no-mips16'` turns off this option.
`-m4650`
`-no-m4650`
  Generate code for the MIPS R4650 chip. This tells the assembler to accept the ``mad'` and ``madu'` instruction, and to not schedule ``nop'` instructions around accesses to the ``HI'` and ``LO'` registers. ``-no-m4650'` turns off this option.
`-m4010`
`-no-m4010`
  Generate code for the LSI R4010 chip. This tells the assembler to accept the R4010 specific instructions (``addciu'`, ``ffc'`, etc.), and to not schedule ``nop'` instructions around accesses to the ``HI'` and ``LO'` registers. ``-no-m4010'` turns off this option.
`-mcpu=CPU`
  Generate code for a particular MIPS cpu. This has little effect on the assembler, but it is passed by `gcc`.
`-nocpp`
  This option is ignored. It is accepted for command-line compatibility with other assemblers, which use it to turn off C style preprocessing. With GNU `as`, there is no need for ``-nocpp'`, because the GNU assembler itself never runs the C preprocessor.
`--trap`
`--no-break`
  `as` automatically macro expands certain division and multiplication instructions to check for overflow and division by zero. This option causes `as` to generate code to take a trap exception rather than a break exception when an error is detected. The trap instructions are only supported at Instruction Set Architecture level 2 and higher.
`--break`
`--no-trap`
  Generate code to take a break exception rather than a trap exception when an error is detected. This is the default.

### 8.13.2 MIPS ECOFF object code

Assembling for a MIPS ECOFF target supports some additional sections besides the usual `.text`, `.data` and `.bss`. The additional sections are `.rdata`, used for read-only data, `.sdata`, used for small data, and `.sbss`, used for small common objects.

When assembling for ECOFF, the assembler uses the `$gp` (`$28`) register to form the address of a "small object". Any object in the `.sdata` or `.sbss` sections is considered "small" in this sense. For external objects, or for objects in the `.bss` section, you can use the `gcc` ``-G'` option to control the size of objects addressed via `$gp`; the default value is 8, meaning that a reference to any object eight bytes or smaller uses `$gp`. Passing ``-G 0'` to `as` prevents it from using the `$gp` register on the basis of object size (but the assembler uses `$gp` for objects in `.sdata` or `sbss` in any case). The size of an object in the `.bss` section is set by the `.comm` or `.lcomm` directive that defines it. The size of an external object may be set with the `.extern` directive. For example, ``.extern sym,4'` declares that the object at `sym` is 4 bytes in length, whie leaving `sym` otherwise undefined.

Using small ECOFF objects requires linker support, and assumes that the `$gp` register is correctly initialized (normally done automatically by the startup code). MIPS ECOFF assembly code must not modify the `$gp` register.

### 8.13.3 Directives for debugging information

MIPS ECOFF `as` supports several directives used for generating debugging information which are not support by traditional MIPS assemblers. These are `.def`, `.endef`, `.dim`, `.file`, `.scl`, `.size`, `.tag`, `.type`, `.val`, `.stabd`, `.stabn`, and `.stabs`. The debugging information generated by the three `.stab` directives can only be read by GDB, not by traditional MIPS debuggers (this enhancement is required to fully support C++ debugging). These directives are primarily used by compilers, not assembly language programmers!

### 8.13.4 Directives to override the ISA level

GNU `as` supports an additional directive to change the MIPS Instruction Set Architecture level on the fly: `.set mipsn`. n should be a number from 0 to 4. A value from 1 to 4 makes the assembler accept instructions for the corresponding ISA level, from that point on in the assembly. `.set mipsn` affects not only which instructions are permitted, but also how certain macros are expanded. `.set mips0` restores the ISA level to its original level: either the level you selected with command line options, or the default for your configuration. You can use this feature to permit specific R4000 instructions while assembling in 32 bit mode. Use this directive with care!

The directive ``.set mips16'` puts the assembler into MIPS 16 mode, in which it will assemble instructions for the MIPS 16 processor. Use ``.set nomips16'` to return to normal 32 bit mode.

Traditional MIPS assemblers do not support this directive.

### 8.13.5 Directives for extending MIPS 16 bit instructions

By default, MIPS 16 instructions are automatically extended to 32 bits when necessary. The directive ``.set noautoextend'` will turn this off. When ``.set noautoextend'` is in effect, any 32 bit instruction must be explicitly extended with the ``.e'` modifier (e.g., ``li.e $4,1000'`). The directive ``.set autoextend'` may be used to once again automatically extend instructions when necessary.

This directive is only meaningful when in MIPS 16 mode. Traditional MIPS assemblers do not support this directive.

### 8.13.6 Directive to mark data as an instruction

The `.insn` directive tells `as` that the following data is actually instructions. This makes a difference in MIPS 16 mode: when loading the address of a label which precedes instructions, `as` automatically adds 1 to the value, so that jumping to the loaded address will do the right thing.

### 8.13.7 Directives to save and restore options

The directives `.set push` and `.set pop` may be used to save and restore the current settings for all the options which are controlled by `.set`. The `.set push` directive saves the current settings on a stack. The `.set pop` directive pops the stack and restores the settings.

These directives can be useful inside an macro which must change an option such as the ISA level or instruction reordering but does not want to change the state of the code which invoked the macro.

Traditional MIPS assemblers do not support these directives.

## 8.14 Hitachi SH Dependent Features

### 8.14.1 Options

`as` has no additional command-line options for the Hitachi SH family.

### 8.14.2 Syntax

#### 8.14.2.1 Special Characters

``!'` is the line comment character.

You can use ``;'` instead of a newline to separate statements.

Since ``$'` has no special meaning, you may use it in symbol names.

#### 8.14.2.2 Register Names

You can use the predefined symbols ``r0'`, ``r1'`, ``r2'`, ``r3'`, ``r4'`, ``r5'`, ``r6'`, ``r7'`, ``r8'`, ``r9'`, ``r10'`, ``r11'`, ``r12'`, ``r13'`, ``r14'`, and ``r15'` to refer to the SH registers.

The SH also has these control registers:

`pr`
  procedure register (holds return address)
`pc`
  program counter
`mach`
`macl`
  high and low multiply accumulator registers
`sr`
  status register
`gbr`
  global base register
`vbr`
  vector base register (for interrupt vectors)

#### 8.14.2.3 Addressing Modes

`as` understands the following addressing modes for the SH. `Rn` in the following refers to any of the numbered registers, but not the control registers.

`Rn`
  Register direct
`@Rn`
  Register indirect
`@-Rn`
  Register indirect with pre-decrement
`@Rn+`
  Register indirect with post-increment
`@(disp, Rn)`
  Register indirect with displacement
`@(R0, Rn)`
  Register indexed
`@(disp, GBR)`
  `GBR` offset
`@(R0, GBR)`
  GBR indexed
`addr`
`@(disp, PC)`
  PC relative address (for branch or for addressing memory). The `as` implementation allows you to use the simpler form addr anywhere a PC relative address is called for; the alternate form is supported for compatibility with other assemblers.
`#imm`
  Immediate data

### 8.14.3 Floating Point

The SH family has no hardware floating point, but the `.float` directive generates IEEE floating-point numbers for compatibility with other development tools.

### 8.14.4 SH Machine Directives

`uaword`
`ualong`
  `as` will issue a warning when a misaligned `.word` or `.long` directive is used. You may use `.uaword` or `.ualong` to indicate that the value is intentionally misaligned.

### 8.14.5 Opcodes

For detailed information on the SH machine instruction set, see SH-Microcomputer User's Manual (Hitachi Micro Systems, Inc.).

`as` implements all the standard SH opcodes. No additional pseudo-instructions are needed on this family. Note, however, that because `as` supports a simpler form of PC-relative addressing, you may simply write (for example)

    mov.l  bar,r0

where other assemblers might require an explicit displacement to `bar` from the program counter:

    mov.l  @(disp, PC)

## 8.15 SPARC Dependent Features

### 8.15.1 Options

The SPARC chip family includes several successive levels, using the same core instruction set, but including a few additional instructions at each level. There are exceptions to this however. For details on what instructions each variant supports, please see the chip's architecture reference manual.

By default, `as` assumes the core instruction set (SPARC v6), but "bumps" the architecture level as needed: it switches to successively higher architectures as it encounters instructions that only exist in the higher levels.

If not configured for SPARC v9 (`sparc64-*-*`) GAS will not bump passed sparclite by default, an option must be passed to enable the v9 instructions.

GAS treats sparclite as being compatible with v8, unless an architecture is explicitly requested. SPARC v9 is always incompatible with sparclite.

`-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite`
`-Av8plus | -Av8plusa | -Av9 | -Av9a`
  Use one of the ``-A'` options to select one of the SPARC architectures explicitly. If you select an architecture explicitly, `as` reports a fatal error if it encounters an instruction or feature requiring an incompatible or higher level. ``-Av8plus'` and ``-Av8plusa'` select a 32 bit environment. ``-Av9'` and ``-Av9a'` select a 64 bit environment and are not available unless GAS is explicitly configured with 64 bit environment support. ``-Av8plusa'` and ``-Av9a'` enable the SPARC V9 instruction set with UltraSPARC extensions.
`-xarch=v8plus | -xarch=v8plusa`
  For compatibility with the Solaris v9 assembler. These options are equivalent to -Av8plus and -Av8plusa, respectively.
`-bump`
  Warn whenever it is necessary to switch to another level. If an architecture level is explicitly requested, GAS will not issue warnings until that level is reached, and will then bump the level as required (except between incompatible levels).
`-32 | -64`
  Select the word size, either 32 bits or 64 bits. These options are only available with the ELF object file format, and require that the necessary BFD support has been included.

### 8.15.2 Enforcing aligned data

SPARC GAS normally permits data to be misaligned. For example, it permits the `.long` pseudo-op to be used on a byte boundary. However, the native SunOS and Solaris assemblers issue an error when they see misaligned data.

You can use the `--enforce-aligned-data` option to make SPARC GAS also issue an error about misaligned data, just as the SunOS and Solaris assemblers do.

The `--enforce-aligned-data` option is not the default because gcc issues misaligned data pseudo-ops when it initializes certain packed data structures (structures defined using the `packed` attribute). You may have to assemble with GAS in order to initialize packed data structures in your own code.

### 8.15.3 Floating Point

The Sparc uses IEEE floating-point numbers.

### 8.15.4 Sparc Machine Directives

The Sparc version of `as` supports the following additional machine directives:

`.align`
  This must be followed by the desired alignment in bytes.
`.common`
  This must be followed by a symbol name, a positive number, and `"bss"`. This behaves somewhat like `.comm`, but the syntax is different.
`.half`
  This is functionally identical to `.short`.
`.proc`
  This directive is ignored. Any text following it on the same line is also ignored.
`.reserve`
  This must be followed by a symbol name, a positive number, and `"bss"`. This behaves somewhat like `.lcomm`, but the syntax is different.
`.seg`
  This must be followed by `"text"`, `"data"`, or `"data1"`. It behaves like `.text`, `.data`, or `.data 1`.
`.skip`
  This is functionally identical to the `.space` directive.
`.word`
  On the Sparc, the `.word` directive produces 32 bit values, instead of the 16 bit values it produces on many other machines.
`.xword`
  On the Sparc V9 processor, the `.xword` directive produces 64 bit values.

## 8.16 Z8000 Dependent Features

The Z8000 as supports both members of the Z8000 family: the unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with 24 bit addresses.

When the assembler is in unsegmented mode (specified with the `unsegm` directive), an address takes up one word (16 bit) sized register. When the assembler is in segmented mode (specified with the `segm` directive), a 24-bit address takes up a long (32 bit) register. See section 8.16.3 Assembler Directives for the Z8000, for a list of other Z8000 specific assembler directives.

### 8.16.1 Options

`as` has no additional command-line options for the Zilog Z8000 family.

### 8.16.2 Syntax

#### 8.16.2.1 Special Characters

``!'` is the line comment character.

You can use ``;'` instead of a newline to separate statements.

#### 8.16.2.2 Register Names

The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer to different sized groups of registers by register number, with the prefix ``r'` for 16 bit registers, ``rr'` for 32 bit registers and ``rq'` for 64 bit registers. You can also refer to the contents of the first eight (of the sixteen 16 bit registers) by bytes. They are named ``rnh'` and ``rnl'`.

    byte registers
    r0l r0h r1h r1l r2h r2l r3h r3l
    r4h r4l r5h r5l r6h r6l r7h r7l

    word registers
    r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15

    long word registers
    rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14

    quad word registers
    rq0 rq4 rq8 rq12

#### 8.16.2.3 Addressing Modes

as understands the following addressing modes for the Z8000:

`rn`
  Register direct
`@rn`
  Indirect register
`addr`
  Direct: the 16 bit or 24 bit address (depending on whether the assembler is in segmented or unsegmented mode) of the operand is in the instruction.
`address(rn)`
  Indexed: the 16 or 24 bit address is added to the 16 bit register to produce the final address in memory of the operand.
`rn(#imm)`
  Base Address: the 16 or 24 bit register is added to the 16 bit sign extended immediate displacement to produce the final address in memory of the operand.
`rn(rm)`
  Base Index: the 16 or 24 bit register rn is added to the sign extended 16 bit index register rm to produce the final address in memory of the operand.
`#xx`
  Immediate data xx.

### 8.16.3 Assembler Directives for the Z8000

The Z8000 port of as includes these additional assembler directives, for compatibility with other Z8000 assemblers. As shown, these do not begin with ``.'` (unlike the ordinary as directives).

`segm`
  Generates code for the segmented Z8001.
`unsegm`
  Generates code for the unsegmented Z8002.
`name`
  Synonym for `.file`
`global`
  Synonym for `.global`
`wval`
  Synonym for `.word`
`lval`
  Synonym for `.long`
`bval`
  Synonym for `.byte`
`sval`
  Assemble a string. `sval` expects one string literal, delimited by single quotes. It assembles each byte of the string into consecutive addresses. You can use the escape sequence ``%xx'` (where xx represents a two-digit hexadecimal number) to represent the character whose ASCII value is xx. Use this feature to describe single quote and other characters that may not appear in string literals as themselves. For example, the C statement ``char *a = "he said \"it's 50% off\"";'` is represented in Z8000 assembly language (shown with the assembler output in hex at the left) as @begingroup @let@nonarrowing=@comment

      68652073    sval    'he said %22it%27s 50%25 off%22%00'
      61696420
      22697427
      73203530
      25206F66
      662200

  @endgroup
`rsect`
  synonym for `.section`
`block`
  synonym for `.space`
`even`
  special case of `.align`; aligns output to even byte boundary.

### 8.16.4 Opcodes

For detailed information on the Z8000 machine instruction set, see Z8000 Technical Manual.

## 8.17 VAX Dependent Features

### 8.17.1 VAX Command-Line Options

The Vax version of `as` accepts any of the following options, gives a warning message that the option was ignored and proceeds. These options are for compatibility with scripts designed for other people's assemblers.

``-D` (Debug)`
``-S` (Symbol Table)`
``-T` (Token Trace)`
  These are obsolete options used to debug old assemblers.
``-d` (Displacement size for JUMPs)`
  This option expects a number following the ``-d'`. Like options that expect filenames, the number may immediately follow the ``-d'` (old standard) or constitute the whole of the command line argument that follows ``-d'` (GNU standard).
``-V` (Virtualize Interpass Temporary File)`
  Some other assemblers use a temporary file. This option commanded them to keep the information in active memory rather than in a disk file. `as` always does this, so this option is redundant.
``-J` (JUMPify Longer Branches)`
  Many 32-bit computers permit a variety of branch instructions to do the same job. Some of these instructions are short (and fast) but have a limited range; others are long (and slow) but can branch anywhere in virtual memory. Often there are 3 flavors of branch: short, medium and long. Some other assemblers would emit short and medium branches, unless told by this option to emit short and long branches.
``-t` (Temporary File Directory)`
  Some other assemblers may use a temporary file, and this option takes a filename being the directory to site the temporary file. Since `as` does not use a temporary disk file, this option makes no difference. ``-t'` needs exactly one filename.

The Vax version of the assembler accepts additional options when compiled for VMS:

``-h n'`
  External symbol or section (used for global variables) names are not case sensitive on VAX/VMS and always mapped to upper case. This is contrary to the C language definition which explicitly distinguishes upper and lower case. To implement a standard conforming C compiler, names must be changed (mapped) to preserve the case information. The default mapping is to convert all lower case characters to uppercase and adding an underscore followed by a 6 digit hex value, representing a 24 digit binary value. The one digits in the binary value represent which characters are uppercase in the original symbol name. The ``-h n'` option determines how we map names. This takes several values. No ``-h'` switch at all allows case hacking as described above. A value of zero (``-h0'`) implies names should be upper case, and inhibits the case hack. A value of 2 (``-h2'`) implies names should be all lower case, with no case hack. A value of 3 (``-h3'`) implies that case should be preserved. The value 1 is unused. The `-H` option directs `as` to display every mapped symbol during assembly. Symbols whose names include a dollar sign ``$'` are exceptions to the general name mapping. These symbols are normally only used to reference VMS library names. Such symbols are always mapped to upper case.
``-+'`
  The ``-+'` option causes `as` to truncate any symbol name larger than 31 characters. The ``-+'` option also prevents some code following the ``_main'` symbol normally added to make the object file compatible with Vax-11 "C".
``-1'`
  This option is ignored for backward compatibility with `as` version 1.x.
``-H'`
  The ``-H'` option causes `as` to print every symbol which was changed by case mapping.

### 8.17.2 VAX Floating Point

Conversion of flonums to floating point is correct, and compatible with previous assemblers. Rounding is towards zero if the remainder is exactly half the least significant bit.

`D`, `F`, `G` and `H` floating point formats are understood.

Immediate floating literals (e.g. ``S`$6.9'`) are rendered correctly. Again, rounding is towards zero in the boundary case.

The `.float` directive produces `f` format numbers. The `.double` directive produces `d` format numbers.

### 8.17.3 Vax Machine Directives

The Vax version of the assembler supports four directives for generating Vax floating point constants. They are described in the table below.

`.dfloat`
  This expects zero or more flonums, separated by commas, and assembles Vax `d` format 64-bit floating point constants.
`.ffloat`
  This expects zero or more flonums, separated by commas, and assembles Vax `f` format 32-bit floating point constants.
`.gfloat`
  This expects zero or more flonums, separated by commas, and assembles Vax `g` format 64-bit floating point constants.
`.hfloat`
  This expects zero or more flonums, separated by commas, and assembles Vax `h` format 128-bit floating point constants.

### 8.17.4 VAX Opcodes

All DEC mnemonics are supported. Beware that `case...` instructions have exactly 3 operands. The dispatch table that follows the `case...` instruction should be made with `.word` statements. This is compatible with all unix assemblers we know of.

### 8.17.5 VAX Branch Improvement

Certain pseudo opcodes are permitted. They are for branch instructions. They expand to the shortest branch instruction that reaches the target. Generally these mnemonics are made by substituting ``j'` for ``b'` at the start of a DEC mnemonic. This feature is included both for compatibility and to help compilers. If you do not need this feature, avoid these opcodes. Here are the mnemonics, and the code they can expand into.

`jbsb`
  ``Jsb'` is already an instruction mnemonic, so we chose ``jbsb'`.
  (byte displacement)
    `bsbb ...`
  (word displacement)
    `bsbw ...`
  (long displacement)
    `jsb ...`
`jbr`
`jr`
  Unconditional branch.
  (byte displacement)
    `brb ...`
  (word displacement)
    `brw ...`
  (long displacement)
    `jmp ...`
`jCOND`
  COND may be any one of the conditional branches `neq`, `nequ`, `eql`, `eqlu`, `gtr`, `geq`, `lss`, `gtru`, `lequ`, `vc`, `vs`, `gequ`, `cc`, `lssu`, `cs`. COND may also be one of the bit tests `bs`, `bc`, `bss`, `bcs`, `bsc`, `bcc`, `bssi`, `bcci`, `lbs`, `lbc`. NOTCOND is the opposite condition to COND.
  (byte displacement)
    `bCOND ...`
  (word displacement)
    `bNOTCOND foo ; brw ... ; foo:`
  (long displacement)
    `bNOTCOND foo ; jmp ... ; foo:`
`jacbX`
  X may be one of `b d f g h l w`.
  (word displacement)
    `OPCODE ...`
  (long displacement)

        OPCODE ..., foo ;
        brb bar ;
        foo: jmp ... ;
        bar:

`jaobYYY`
  YYY may be one of `lss leq`.
`jsobZZZ`
  ZZZ may be one of `geq gtr`.
  (byte displacement)
    `OPCODE ...`
  (word displacement)

        OPCODE ..., foo ;
        brb bar ;
        foo: brw destination ;
        bar:

  (long displacement)

        OPCODE ..., foo ;
        brb bar ;
        foo: jmp destination ;
        bar:

`aobleq`
`aoblss`
`sobgeq`
`sobgtr`
  (byte displacement)
    `OPCODE ...`
  (word displacement)

        OPCODE ..., foo ;
        brb bar ;
        foo: brw destination ;
        bar:

  (long displacement)

        OPCODE ..., foo ;
        brb bar ;
        foo: jmp destination ;
        bar:

### 8.17.6 VAX Operands

The immediate character is ``$'` for Unix compatibility, not ``#'` as DEC writes it.

The indirect character is ``*'` for Unix compatibility, not ``@'` as DEC writes it.

The displacement sizing character is ```'` (an accent grave) for Unix compatibility, not ``^'` as DEC writes it. The letter preceding ```'` may have either case. ``G'` is not understood, but all other letters (`b i l s w`) are understood.

Register names understood are `r0 r1 r2 ... r15 ap fp sp pc`. Upper and lower case letters are equivalent.

For instance

    tstb *w`$4(r5)

Any expression is permitted in an operand. Operands are comma separated.

### 8.17.7 Not Supported on VAX

Vax bit fields can not be assembled with `as`. Someone can add the required code if they really need it.

## 8.18 v850 Dependent Features

### 8.18.1 Options

`as` supports the following additional command-line options for the V850 processor family:

`-wsigned_overflow`
  Causes warnings to be produced when signed immediate values overflow the space available for then within their opcodes. By default this option is disabled as it is possible to receive spurious warnings due to using exact bit patterns as immediate constants.
`-wunsigned_overflow`
  Causes warnings to be produced when unsigned immediate values overflow the space available for then within their opcodes. By default this option is disabled as it is possible to receive spurious warnings due to using exact bit patterns as immediate constants.
`-mv850`
  Specifies that the assembled code should be marked as being targeted at the V850 processor. This allows the linker to detect attempts to link such code with code assembled for other processors.
`-mv850e`
  Specifies that the assembled code should be marked as being targeted at the V850E processor. This allows the linker to detect attempts to link such code with code assembled for other processors.
`-mv850any`
  Specifies that the assembled code should be marked as being targeted at the V850 processor but support instructions that are specific to the extended variants of the process. This allows the production of binaries that contain target specific code, but which are also intended to be used in a generic fashion. For example libgcc.a contains generic routines used by the code produced by GCC for all versions of the v850 architecture, together with support routines only used by the V850E architecture.

### 8.18.2 Syntax

#### 8.18.2.1 Special Characters

``#'` is the line comment character.

#### 8.18.2.2 Register Names

`as` supports the following names for registers:

`general register 0`
  r0, zero
`general register 1`
  r1
`general register 2`
  r2, hp
`general register 3`
  r3, sp
`general register 4`
  r4, gp
`general register 5`
  r5, tp
`general register 6`
  r6
`general register 7`
  r7
`general register 8`
  r8
`general register 9`
  r9
`general register 10`
  r10
`general register 11`
  r11
`general register 12`
  r12
`general register 13`
  r13
`general register 14`
  r14
`general register 15`
  r15
`general register 16`
  r16
`general register 17`
  r17
`general register 18`
  r18
`general register 19`
  r19
`general register 20`
  r20
`general register 21`
  r21
`general register 22`
  r22
`general register 23`
  r23
`general register 24`
  r24
`general register 25`
  r25
`general register 26`
  r26
`general register 27`
  r27
`general register 28`
  r28
`general register 29`
  r29
`general register 30`
  r30, ep
`general register 31`
  r31, lp
`system register 0`
  eipc
`system register 1`
  eipsw
`system register 2`
  fepc
`system register 3`
  fepsw
`system register 4`
  ecr
`system register 5`
  psw
`system register 16`
  ctpc
`system register 17`
  ctpsw
`system register 18`
  dbpc
`system register 19`
  dbpsw
`system register 20`
  ctbp

### 8.18.3 Floating Point

The V850 family uses IEEE floating-point numbers.

### 8.18.4 V850 Machine Directives

`.offset <expression>`
  Moves the offset into the current section to the specified amount.
`.section "name", <type>`
  This is an extension to the standard .section directive. It sets the current section to be <type> and creates an alias for this section called "name".
`.v850`
  Specifies that the assembled code should be marked as being targeted at the V850 processor. This allows the linker to detect attempts to link such code with code assembled for other processors.
`.v850e`
  Specifies that the assembled code should be marked as being targeted at the V850E processor. This allows the linker to detect attempts to link such code with code assembled for other processors.

### 8.18.5 Opcodes

`as` implements all the standard V850 opcodes.

`as` also implements the following pseudo ops:

`hi0()`
  Computes the higher 16 bits of the given expression and stores it into the immediate operand field of the given instruction. For example: ``mulhi hi0(here - there), r5, r6'` computes the difference between the address of labels 'here' and 'there', takes the upper 16 bits of this difference, shifts it down 16 bits and then mutliplies it by the lower 16 bits in register 5, putting the result into register 6.
`lo()`
  Computes the lower 16 bits of the given expression and stores it into the immediate operand field of the given instruction. For example: ``addi lo(here - there), r5, r6'` computes the difference between the address of labels 'here' and 'there', takes the lower 16 bits of this difference and adds it to register 5, putting the result into register 6.
`hi()`
  Computes the higher 16 bits of the given expression and then adds the value of the most significant bit of the lower 16 bits of the expression and stores the result into the immediate operand field of the given instruction. For example the following code can be used to compute the address of the label 'here' and store it into register 6: ``movhi hi(here), r0, r6'` ``movea lo(here), r6, r6'` The reason for this special behaviour is that movea performs a sign extention on its immediate operand. So for example if the address of 'here' was 0xFFFFFFFF then without the special behaviour of the hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6, then the movea instruction would takes its immediate operand, 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it into r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E). With the hi() pseudo op adding in the top bit of the lo() pseudo op, the movhi instruction actually stores 0 into r6 (0xFFFF + 1 = 0x0000), so that the movea instruction stores 0xFFFFFFFF into r6 - the right value.
`hilo()`
  Computes the 32 bit value of the given expression and stores it into the immediate operand field of the given instruction (which must be a mov instruction). For example: ``mov hilo(here), r6'` computes the absolute address of label 'here' and puts the result into register 6.
`sdaoff()`
  Computes the offset of the named variable from the start of the Small Data Area (whoes address is held in register 4, the GP register) and stores the result as a 16 bit signed value in the immediate operand field of the given instruction. For example: ``ld.w sdaoff(_a_variable)[gp],r6'` loads the contents of the location pointed to by the label '_a_variable' into register 6, provided that the label is located somewhere within +/- 32K of the address held in the GP register. [Note the linker assumes that the GP register contains a fixed address set to the address of the label called '__gp'. This can either be set up automatically by the linker, or specifically set by using the ``--defsym __gp=<value>'` command line option].
`tdaoff()`
  Computes the offset of the named variable from the start of the Tiny Data Area (whoes address is held in register 30, the EP register) and stores the result as a 4,5, 7 or 8 bit unsigned value in the immediate operand field of the given instruction. For example: ``sld.w tdaoff(_a_variable)[ep],r6'` loads the contents of the location pointed to by the label '_a_variable' into register 6, provided that the label is located somewhere within +256 bytes of the address held in the EP register. [Note the linker assumes that the EP register contains a fixed address set to the address of the label called '__ep'. This can either be set up automatically by the linker, or specifically set by using the ``--defsym __ep=<value>'` command line option].
`zdaoff()`
  Computes the offset of the named variable from address 0 and stores the result as a 16 bit signed value in the immediate operand field of the given instruction. For example: ``movea zdaoff(_a_variable),zero,r6'` puts the address of the label '_a_variable' into register 6, assuming that the label is somewhere within the first 32K of memory. (Strictly speaking it also possible to access the last 32K of memory as well, as the offsets are signed).
`ctoff()`
  Computes the offset of the named variable from the start of the Call Table Area (whoes address is helg in system register 20, the CTBP register) and stores the result a 6 or 16 bit unsigned value in the immediate field of then given instruction or piece of data. For example: ``callt ctoff(table_func1)'` will put the call the function whoes address is held in the call table at the location labeled 'table_func1'.

For information on the V850 instruction set, see V850 Family 32-/16-Bit single-Chip Microcontroller Architecture Manual from NEC. Ltd.

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