Main Index
SuperSIM Help Contents

Introduction---What is SuperSIM?

Using SuperSIM with SuperCAD

Reference

Detailed description of the simulator netlist, part models, logic primitives, analysis commands, and others.

Technical Support


Technical Support

Technical support can be obtained by calling or writing Mental Automation at:

5415 136th Place SE

Bellevue WA 98006

(206) 641-2141

(206) 649-0767 (FAX)


Introduction

The SuperSIM digital simulator allows you to easily develop and checkout a circuit design before you actually build it. You can draw up a schematic with SuperCAD, extract the netlist, and run a simulation from the UTILITIES menu. After the simulation, you can then probe various signals using the logic analyzer popout display. The whole process is completely automatic, and is done entirely within the SuperCAD environment. You are free to treat your design as though it were implemented on a virtual breadboard, which you can test using virtual instruments (the logic analyzer display in this case). You can easily alter portions of the circuit or make corrections and then re-run the simulation to see the effects. Using a 386 or greater machine with a hard disk, the process of changing the circuit and seeing the result can be measured in seconds for a small to medium sized circuit.

SuperSIM is great at checking out circuits such as the following:

 counters

 sequencers

 peripheral device interfaces

 microprocessor interfaces

 state machines

Basically you can simulate anything that is made up out of TTL 74xxx or CMOS 4xxx logic---or anything that can be drawn as combinational logic and flip-flops.


Using SuperSIM with SuperCAD

SuperSIM is an add-on module to the schematic editor SuperCAD. To run SuperSIM, you must have SuperCAD both to draw the circuit being simulated and to view the circuit waveforms which are output from the simulation.

The operation of SuperCAD with SuperSIM is described in the following topics:

Preparation of a Schematic for Simulation

Referencing and Using External Library Models

Running and Viewing the Simulation Results

The Pattern Generator

Virtual Display Devices


Preparation of Schematic for Simulation
Preparation of a Schematic for Simulation

SuperSIM works best with small to medium-complexity digital circuits which can fit on a single sheet. You can work with multiple sheets but you may have to switch from one sheet to another to view different signals. The steps for preparing a schematic for simulation are as follows:

a) Draw the schematic----be sure you use parts that are in the SuperSIM library (see the files---TTL.LIB and CMOS.LIB). You can also use resistors to tie input lines to a logic HIGH. Do not use any analog parts or discretes such, as transistors, capacitors and inductors (use SuperSPICE for analog designs).

b) Mark all signals to be probed (traced) in the simulation by using the MARK operation in the DISPLAY pulldown menu. You first have to click over MARK and then click over any signal which is to be probed (you can remove a signal by clicking so that the asterisk disappears).

c) Provide a circuit input stimulus---this can be as simple as a single clock signal. To provide the signal simply place the PATGEN (pattern generator) symbol on the schematic and wire it to the input point.

d) The default for all circuit delays is 0; to change this, simply specify a different delay in the GLOBAL DELAY item in the digital simulator setup. To change the delay for just one circuit type , type the #.DELAY statement on the schematic; for example:

#.DELAY D74163 6

e) If you want to observe single step behavior of the circuit add virtual display symbols such as the DLED or HEX display symbol. The terminals of these symbols should be wired to nets with named, marked signals (for example, RD*).

f) Add any special commands (such as a .LIB command or .INIT_LO command ) to the schematic using the text operation; these commands should be preceded by the # character.

Note that you should use the DIP pinout option (the default) when drawing the schematics, as the simulator models are based on DIP package pinouts. You could use the simulator with the surface mount package pinouts, but you would have to edit the SuperSIM library models to accommodate the different pinout.

An example schematic, which is ready for simulation, is shown in the following (COUNTER example):

The clock input signal XCLK has a time step of 5ns (nanoseconds); that is it is low(L) for 5ns, and then high(H) for 5ns. The 74192 counter is cleared with the signal XCLR. With the logic shown, the counter counts up to state 7 (where QA, QB, and QC are all high) and then produces a pulse through the 4-input 7420 NAND gate. The pulse is also produced every 10 clock cycles.

If you run SuperSIM, the logic analyzer display is as follows:


Running and Viewing the Simulation Results

Once the schematic is prepared  (see Preparation of a Schematic for Simulation) click on DIGITAL SIMULATION in the UTILTIES menu, and a dialog box will appear, as follows:

Click on the SETUP button to establish the duration of the simulation and other items:

After entering the values, then click on the YES button  of the starting dialog to initiate operation. The SuperCAD netlister will first run to produce a netlist in digital simulator format. The netlister produces a SuperSIM input file with the name of the current schematic as the root name and the extension .CKT. Next,SuperSIM itself is run. During the simulation, SuperSIM displays a window indicating progress in the simulation. At the conclusion of the simulation, you can view the latest simulation results by clicking over the DISPLAY menu and then clicking over the ANALYZE function. This brings up the logic analyzer display window. Trace signals are automatically loaded into the display when it is activated. You can move the window over the circuit, so that it doesn't obscure the signals of interest, by dragging over the title bar.

To show the time display of a specific signal, you can also click over any of the trace labels and then click over any marked signal on the schematic. Marked signals are indicated by a "*" suffix. Up to 200 samples per channel are loaded from the trace buffer file on disk when a given signal is accessed. Note that 200 samples can correspond to a much larger number of time samples, since the simulator is event driven and records outputs only if they change. For examples of this, see the .LST output files generated by the examples provided with the software.

If the schematic includes virtual display devices such as LEDS, the HEX display or the RELAY symbol, you can look at the circuit behavior using the STEP CONTROL dialog. This dialog allows you to single step the circuit or animate it for a specified number of clock steps

For more information on displaying waveforms you can also see the topic Logic Analyzer Display; for information on watching the state of a circuit using virtual LEDS and other display devices see the topic Step Control Dialog.


Logic Analyzer Display

This display window is accessed by clicking over the ANALYZE box in the DISPLAY menu in SuperCAD, and allows you to view up to 16 channels of time waveforms.

The window can be moved by dragging over the window title bar. Control over the timebase of the scope is accomplished by clicking over the TIME button.The direction of the time-scale magnification or contraction is specified by the direction control button; this is the square button to the right of the TIME button, and it is labeled either with a + or a -. If the direction control button displays +, then each click increases the time per division, otherwise(when the direction control button displays -), it decreases the time. To view different portions of the display, use the scroll bar or arrow keys.

Traces are automatically loaded and displayed in the window at the conclusion of a simulation run. They are also loaded and displayed if the current  schematic has an associated .LST file (indicating that a simulation was previously made). You can display a waveform in just one channel by clicking over one of the display labels, and then clicking over a marked signal name on the schematic. If a given node on the circuit doesn't have a name, you have to add one, and then re-run the simulator.

You can read out the time at a point on a waveform by using the readout cursor (the vertical line). This cursor is moved by using the mouse to drag the line.

A screen dump of the logic analyzer window can be made by clicking over the PRINT button.  This results in the following dialog:

Click on the setup button to make any changes in the printer setup or paper orientation..


Timebase Button

Use to step time base units.


Print Button

Use to print display area.


Scrollbar Control

Use to scroll waveform display.


Up/Down Control

Use to control direction of gain step or timebase step.


Gain Control Button

Use to step gain units.


Offset Control

Use to move waveform up or down.


Label Field

Shows name of signal; click on to access new signal.


Step Control Dialog

This dialog is accessed by clicking over the STEP menu item in the DISPLAY menu in SuperCAD, and allows you to monitor the state of the circuit through use of virtual display devices such as LEDS, HEX displays and RELAY parts. The dialog is shown below:

To step the circuit one clock (which is the highest rate clock in the circuit), click on the STEP button. This will update all the display devices in the circuit with values for the next clock interval. You can animate the operation by clicking on the CYCLE button; this will step the circuit once every 500ms for N steps, where N is the number of steps specified in the NO. STEPS field of the dialog.

Note that before you can use the step dialog, you must have already made a simulation run on the given circuit. You do this by clicking on Digital Simulation... in the UTILTIES menu.


The Pattern Generator

The pattern generator is used to specify single-bit inputs to a circuit. The symbol is as follows:

To use the symbol and specify what the signal is, simply place it on the schematic and wire it to the input point. Double click on the part for setup. The setup dialog box is as follows:

If you check the REPEATING box, the signal produced from the generator is a clock; otherwise, it is a one-shot input signal. Be sure to enter  a unique non-zero reference designator number in the REFERENCE field.

The time units used in the dialog are established by the SCALE item in the digital simulator setup dialog (see Running and Viewing the Simulation Results). Do not enter units here.


Virtual Display Devices

SuperSIM comes with special symbols which can be used to show the state of a simulated circuit when it is being single stepped or animated. To use the symbols, place them on the circuit and wire them to the output points which are to be monitored; as with other parts they should also be given a non-zero designator number. Note that the output points should have marked signals. After wiring the symbols, run the simulation by clicking on Digital Simulation... in the UTILITIES menu. After this, when you use the STEP dialog, you can view operation of the circuit with the (virtual display device) symbols.

Light-Emitting Diode (DLED)

Hexadecimal Display (VDSIP)

Relay (RELAY)


SuperSIM Reference

Input File Format (.CKT files)

Special First Position Characters

Automatic Globals

Part Models (Macros)

Wire Gates

Test Vectors

Logic Primitives

Default Settings for the Simulator

SuperSIM Libraries

Models Included With SuperSIM

SuperSIM Program Limits


Input File Format (.CKT files)

Circuit definition files are identified by the extension '.ckt', and are produced from a SuperCAD schematic by the netlister. They contain the specifications for building a circuit. Each logical line of the file contains a primitive name, a macro name, or one of the following keywords as its first word:

.Loading--counts the number of inputs connected to each output

.Bus--------grouping of signals for a numeric display

.ROM------builds a rom up to 256 x 32

.Probe*----set of nodes, scales, or buses to be sampled and displayed

.Time*-----sets the maximum simulation time

.Scale*-----sets the value of a time step

.LIB--------selects a model library

.INIT_HI---set all starting values to high (normally unknown)

.INIT_LO--set all starting values to low(normally unknown)

.END*------keyword to mark the end of the circuit file

Click over highlighted keywords for more detailed information.

The character '$' indicates a comment line, which is ignored unless otherwise noted. The first comment line in file will be the title line for the output file. A semicolon will end an input line. Everything after a semicolon is ignored and could also be comments. All blank lines are ignored.

Keywords marked with the asterisk (*) correspond to commands generated automatically from the schematic. The other keywords can be typed directly on the schematic to control the simulation. For example:

#.INIT_LO


.LIB

Netlist statement: .LIB filename[.LIB] [filename] [filename]

 Selects the library file to be searched for any macros used later. There can be up to 10 library files specified. With each library file there will be another file (filename.DIR) in the same directory. If the file .LIB is more up to date than the file.DIR the simulator will remake the library directory file automatically.

SuperSIM automatically looks for the libraries TTL.LIB, CMOS.LIB and MISC.LIB in the SuperCAD subdirectory---you do not have to use the .LIB statement for these. If you want to use models from one of the other libraries, however, (such as the ALS library), then type a statement on the schematic, such as in the following:

#.LIB C:\SUPERCAD\ALS.LIB

This statement will then be placed in the netlist.


.BUS

Netlist statement:  .BUS BUS_NAME  sig15 sig14 .... sig0   (1 to 16 signals)

Allows grouping of signals into a common BUS which can be probed as any other signal. Busses will be in HEX format. Bus_name must not be used as an gate output or external. Signals are grouped MSB first up to 16 max (FFFF).  Bus lines can be extended with the plus character. (+)


.TIME

Netlist statement:  .TIME  n0 n1

 n0 is the end time of the simulation.  max 32767  (simulator steps);  n1 is the step period for the simulation.


.SCALE

Netlist statement:  .SCALE  n.nnnEnn  or n.nnn [base]  (base = ps, ns, us, ms )

 The SCALE command sets the real value of a simulator time step for SuperCAD "logic analyzer" window readout. The number can be in exponential format or in decimal or with an optional base argument. It must range from 1 pico second to 1 second ie. 1e12  to 1.00. One of four time base mnemonics can be supplied: ps, ns, us, ms ( [ps] = 1e12, [ns] = 1e9, [us] = 1e6, [ms] = 1e3).

For example:

.scale 1.5 us

.scale 1.5e6   (the same time step as above)


.PROBE

Netlist statement:  .PROBE  SIGNAL_0 .... SIGNAL_n

 The probe command tell the simulator which signals to monitor. There must be at least one monitored signal or the simulation will abort. There can be as many .PROBE lines as needed up to a total of 128 monitored signals. A period ('.') in the signal list leaves a blank signal line. Probe lines can go anywhere in the file and the same signal(s)  can be monitored as often as required to help display. e.g. clks. Probe lines can be extended with the plus character. (+)

NOTE: The SuperCAD netlister automatically generates this command for any signals marked with a trailing "*"; you do not generally need to use the .PROBE command separately if you are using SuperCAD.


.LOADING

 (lists all circuit outputs with the number of inputs

 connected) Adds into the .LST file.


.ROM

Netlist statement: .ROM [delay] / addr / data / contents

 The ROM command in the simulator, allows up to eight address inputs, with up to 16 data signals and up to 256 locations containing 0FFFF (HEX).

There must be only three slashes in the rom.

Slashes are not allowed in signal names in the rom. Delay is optional. Address and data fields go MSB first. Any missing addr or data assume zero. Contents are entered sequentially starting with the lowest address. Missing contents assume FFFF. The rom can continue over multiple lines. There must be enough bits in the contents to cover all the data signals. ie. 0FFFF will cover 16 signals.

 Rom example: ( 32 * 8 )

 .rom 1 / a4 a3 a2 a1 a0 / d7 d6 d5 d4 d3 d2 d1 d0 /

 + 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f

 + 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f

The binary pattern in the contents of the rom will drive the data outputs of the rom. The address lines are inputs and the data lines are outputs, similar to test vectors. The outputs of the rom must not short to other logic outputs, but can connect to a tristate buffer (such as a 74244) if bussing is required.

 Roms can be used as lookup tables or pattern generators. If the ROM is used as a logical element that is driving other logic inputs then the minimum delay for the part must be 1.


Special First Position Characters

'*'  The asterisk is the start of a macro expansion. See MACROS.

'+'  The plus sign is a continuation of a macro input list. There  can be as many more lines as needed up to a total of 64 inputs  per macro. There can be no other lines between the '*' and  the '+'. Macros can only be defined in a library file.  Important: A macro can not be processed before the library  that the macro is defined in has been loaded with a .LIB  command. All libraries will be searched for the macro  definition.


Automatic Globals

VCC & GND are automatically declared as level one (1) and level zero (0). These signals should not be driven by logic outputs. Also the dummy signal 'NC' is reserved as a no connect signal, and cannot be used except as a no connect signal.


Part Models (Macros)

A macro or substitution block is a collection of components which form a more complex subcircuit.  They are defined using the MACRO and EOM keywords and stored in a parts LIBRARY. Thereafter they can be used multiple times by referring to them by the macro name.  For example:

.MACRO 7400 delay p1 p2 p3 p4 p5 p6 p7

 + p8 p9 p10 p11 p12 p13 p14

 p3  NAND delay p1 p2

 p6  NAND delay p4 p5

 p8  NAND delay p10 p9

 p11 NAND delay p13 p12

 .EOM

Macros cannot be nested.  The formal node names in the macro definition are replaced by actual node names when the macro is used, e.g.

      macro use :

      * U1 7400 3 in1 in2 out1 nc nc nc gnd

      + nc nc nc nc nc nc vcc

      * U2 7400 3 in3 in4 out2 ; Note: missing pins will become NC

There cannot be more tokens passed to a macro than the macro has place holders.


Wire Gates

The WIRE gate is automatically provided on tristate or shorted outputs to allow connection of multiple 3state outputs to a single output node. This is analogous to a real wire, where signals are multiplexed. However, unlike a real wire, the output value remains constant unless driven by a change on the inputs.  Due to leakage, a real wire would eventually float high,low or unknown. Warnings will be given only for non tristate or non resistive outputs that are shorted.

Mixed combinations of the same strength inputs will cause an UNKNOWN output on the wire gate. A combination of the same level of any strength will keep the same output as the input. Different strengths will fight as follows : Driving will win over resistive, resistive will win over high Z. The output of the 'wire' gate will take the strength of the strongest input.

Wired 'OR' elements keep their own propagation delays and the 'wire' itself has zero delay.


Default Settings for the Simulator

The simulator adopts certain default setting when the input arguments are missing.

 start time for a test vector = 0

 step time for a test vector  = 5

 end time for a clk test vector      = end of simulation

 end time for a input test vector    = end of pattern

 end time for a trigger test vector  = end of simulation

 end time for the simulation run     = 100

 edge for a triggered input   = positive


Making test Vectors
Test Vectors

With the latest version of SuperSIM/SuperCAD, test vectors are established by using the PATGEN part in a schematic. Once setup, this part produces netlist statements whose format is described below.

Clock Definitions

A "clock" is any pattern that repeats. The netlist statement is:

signal_name CLK [start_time] [time_step] [end_time] = <pattern>

For example:

ZCLK  0  10  1000 = LH

____------____------____-----

0   10   20   30   40   50   60...

This clock starts at time 0 and a pattern that changes every 10 units; the period of the clock is 20 units.

Input definitions

The netlist statement for an input definition is:

signal_name INPUT [start_time] [time_step] = <pattern field>

For example:

DATA1 INPUT 0 10 = HLHLLLHHHLH

------____------_____________-------------------_____----------

0   10   20   30   40   50   60   70   80   90   100

The pattern field can be up to 32 characters long and must not contain any spaces.


Logic Primitives

Logic primitives have the following syntax:

     output primitivename delay [enable] input (input...)

"output" is the name of the node driven by the logic element. The "primitive name" is a reserved word to the simulator, such as INV, NAND. "delay" is the propagation delay for the logic element and can be zero. "input" is the name of the node or nodes connected to the inputs of the logic primitive. "enable" is the tristate control for the tristate gates and is active high. The propgation delay for a tristate element is independent of the enabled state of the element. The enable element has zero propagation delay. Therefore, the output of the element becomes enabled or disabled as soon as the enable input changes.

NOTE: in the following "-" signifies a don't care input; "*" signifies an unknown input or output

Gates

Inverter

Logic Buffer

And Gate

Or Gate

Nor Gate

Exclusive Or Gate

Exclusive Nor Gate

Resistive and Tristate Gates

Transmission Gate

Flip-flops

D Flip-flop

Data Latch

JK Flip-flop

Other

Multiplexor


Inverter

Netlist statement: output INV delay input

Truth table:

input	output

L	H

H	L

*	*


Buffer

Netlist statement: output BUF delay input

Truth table:

input	output

L	L

H	H

*	*


And gate

Netlist statement: output AND delay input [(input...)]

Truth table:

inputs	outputs

all H 	H

& any*	*

else  	L


Nand gate

Netlist statement: output NAND delay input [(input...)]

Truth table:

inputs	outputs

all H 	L

& any*	*

else  	H


Or gate

Netlist statement: output OR delay input [(input...)]

Truth table:

inputs	outputs

all L 	L

& any*	*

else  	H


Nor gate

Netlist statement: output NOR delay input [(input...)]

Truth table:

inputs	outputs

all L 	H

& any*	*

else	L


Exclusive nor gate

Netlist statement: output XNOR delay input [(input...)]

Truth table:

inputs	outputs

both H	H

both L	H

any*  	*

else  	L


Exclusive or gate

Netlist statement: output XOR delay input [(input...)]

Truth table:

inputs	outputs

both H	L

both L	L

any*  	*

else  	H


Resistive and Tristate Gates

Resistive logic gates are the same as gates but have a resistive output driver. Likewise, tristate gates are the same as gates but with tristate output drivers. The correspondance among the gate element types is as follows:

INV	RINV	TINV

BUF	RBUF	TBUF

AND	RAND	TAND

NAND	RNAND	TNAND

OR	ROR	TOR

NOR	RNOR	TNOR

XOR	RXOR	TXOR

XNOR	RXNOR	TXNOR


Transmission Gates

Transmission gates model switches or digital transistors. Tristate gates are only gates with transmission gates connected to their output. The transmission gate, like the tristate gate automatically goes to a wire gate.

Netlist statement: Q TG delay Q'enable input

Pin names:

enable:	control for the output enable, active high

delay:	propagation delay

input:	input signal to the element

Q, Q':	outputs for the element (Q' is the complement output)

Truth table:

input	enable	outputs

H	H	H

L	H	L

*	H	*

L	tristate

*	*


D Flipflop

Netlist statement: Q DFF delay Q'clock data [set'] [reset'] [/init]

Pin names:

clock:	clock signal to flipflop (positive edge)

delay:	propagation delay

data:	latch input data

set:	sets output to logic 1

reset:	resets output to logic 0

Q, Q':	outputs for the element (Q' is the complement output)

init:	optional initialize control statement (/1 or /0)

Truth table:

D	clock	reset'	set'	Q Q'

L	H	L H

H	L	H L

L	L	* *

H	LH	H	H	H L

L	LH	H	H	L H

*	LH	H	H	* *

*	H	H	* *

L	H	H	no change


Data Latch

Netlist statement: Q MUX delay Q'enable Q D [set'] [reset']

Pin names:

enable:	latch enable (follow data)

delay:	propagation delay

D:	latch input data

set:	sets output to logic 1

reset:	resets output to logic 0

Q..Q':	outputs for the element (matching input)

Truth table:

D  	enable	reset'	set'	Q Q'

 	L	H 	L H

H	L	H L

L	L	* *

L	H	H	no change

L	H	H	H	L H

H	H	H	H	H L

*	H	H	H	* *

Q	*	H	H	no change

else	*	H	H	* *


JK Flipflop

Netlist statement: Q JKFF delay Q'clock J K [set'] [reset'] [/init]

Pin names:

clock:	clock signal to flipflop (positive edge)

delay:	propagation delay

J,K:	latch input data

set:	sets output to logic 1

reset:	resets output to logic 0

Q, Q':	outputs for the element (Q' is the complement output)

init:	optional initialize control statement (/1 or /0)

Truth table:

J	K	clock	reset'	set'	Q Q'

L	L	HL	H	H	no change

L	H	HL	H	H	L H

H	L	HL	H	H	H L

H	H	HL	H	H	toggle

*	HL	H	H	* *

-	*	HL	H	H	* *

*	H	H 	* *

L	H	L H

H      L   	H L

*	* *

*	* *

L	L	* *

NOTE: the TFF flip-flop is the same as a JK flip-flop, but the J and K inputs are tied together.


Multiplexor

Netlist statement: Q MUX delay Q'select inp_a inp_b [set'] [reset'] [/init]

Pin names:

clock:	clock signal to flipflop (positive edge)

delay:	propagation delay

inp_a:	data input a

inp_b:	data input b

select:	selects input

set:	sets output to logic 1

reset:	 resets output to logic 0

Q, Q':	outputs for the element (Q' is the complement output)

init:	optional initialize control statement (/1 or /0)

Truth table:

select	inp_a	inp_b	set'	reset'	Q Q'

L	H	H L

H	L	L H

L	L	* *

L	H	L	H	H	H L

L	L	H	H	H	L H

H	H	L	H	H	L H

H	L	H	H	H	H L

*	H	H	H	H	H L

*	L	L	H	H	L H

*	else H	H	* *

*	* *

*	* *


SuperSIM Libraries

Libraries contain circuit models (macros) for all parts used in a simulation. The libraries can be maintained or modified by the user using any text editor. The libraries have the default extension .LIB but can have any extension name. A directory file with the same root name and the extension .DIR is created automatically if the library is modified or used for the first time.

You can add a macro for a given part by first looking up a description of the part in the vendor's data book. For parts like gates, you only have to know the pinout and find a primitive (such as NAND or XOR) to represent the part. An example of this is the 7400 part listed above. As another example, here is the 7411 AND gate part:

$ triple 3input positive AND gates

.macro 7411 dly p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14

p6 AND dly p3 p4 p5

p8 AND dly p9 p10 p11

p12 AND dly p1 p2 p13

.eom

Note that the pin numbers of the IC are given signal names p<n>, where <n> corresponds to the pin number.

For more complex parts you have to determine the equivalent circuit in terms of the primitives. For many parts the equivalent circuit is provided by the vendor (TI is particularly good about this) in the data book. For example, here is the 7492 (divide by 12) counter part:

$ divide by 12 counter

.macro 7492 dly p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14

n0 NAND 0 p6 p7

p8 TFF dly nc p9 vcc nc n0 /0

p9 JKFF dly n3 p1 p11 vcc nc n0 /0

p11 JKFF dly nc p1 n3 vcc nc n0 /0

p12 TFF dly nc p14 vcc nc n0 /0

.eom

As in the 7411 example the IC pins use the names p1, p2, etc. However, here we also have internal nodes designated as n<n>, where <n> is an interger. n0 is the output of the reset NAND gate which in this case goes to all reset inputs of the flip-flops. The 2nd internal node (n3) goes from the Q' output of the p9 flip-flop to the J input of the p11 flip-flop.

The 7490 counter is slightly more complicated, and has more nodes and gate primitives:

$ decade counter

.macro 7490 dly p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14

n0 NAND 0 p6 p7

n1 NAND 0 p2 p3

n2 AND 0 n1 n0

n3 AND 0 p9 p8

p8 TFF dly nc p9 vcc nc n2 /0

p9 JKFF dly nc p1 n7 vcc nc n2 /0

p11 JKFF dly n7 p1 n3 p11 n0 n1 /0

p12 TFF dly nc p14 vcc n0 n1 /0

.eom

Note in this case that the model has one less gate than the TI manual shows (because 2 gates are doing exactly the same function, but driving different flip-flop reset inputs in the Qb and QC stages), but the model nevertheless functions the same.

See the TTL.LIB file for more examples of models.

See the description of the .LIB statement to reference a library for a given simulation.


SuperSIM Program Limits

equivalent gates	16000

circuit elements	4000

number of signals	500

scheduled events	1024

external inputs	256

monitored outputs	128

macro input tokens	128

number of ROMs	32

number of busses	32

logic primitives	30

name length for signals	20

number of open lib dirs	10


Models Included With SuperSIM

(in basic MA8100 package)

CMOS Models

(25  Macros)

C4000   C4001   C4002   C4006   C4009

C4012   C4013   C4014   C4015   C4020

C4028   C4030   C4040   C4049   C4050

C4060   C4069   C4070   C4077   C4078

C4106   C4502   C4503   C4556   C4572

TTL Models

(125  Macros)

7400    7402    7404    7406    7408

7410    7411    7414    7420    7421

7427    7428    7430    7432    7442

7444    7445    7447    7448    7451

7469    7473    7474    7475    7476

7482    7483    7485    7486    7490

7491    7492    7493    7494    7495

74105   74106   74112   74113   74114

74116   74121   74128   74132   74133

74134   74138   74139   74140   74145

74147   74148   74150   74151   74152

74153   74154   74155   74156   74157

74158   74160   74161   74162   74163

74164   74165   74166   74168   74169

74173   74174   74175   74176   74179

74180   74181   74182   74183   74190

74191   74192   74193   74194   74195

74198   74199   74240   74241   74242

74243   74244   74245   74246   74247

74251   74253   74257   74258   74259

74273   74276   74280   74283   74365

74366   74367   74368   74373   74374

74375   74376   74390   74393   74395

74596   74597   74599   74604   74605

74606   74607   74620   74651   74652

Note: Addtional 400 models available in MA8110 package.