At the heart of every system is the motherboard; you
learned about various motherboards in Chapter 4,
"Motherboards." A motherboard is made up of components. The
major component that determines how the motherboard actually
works is called the bus. In this chapter, you learn about
system buses.
What Is a Bus?
A bus is nothing but a common pathway across which
data can travel within a computer. This pathway is used for
communication and can be established between two or more
computer elements. A PC has many kinds of buses, including the
following:
- Processor bus
- Address bus
- I/O bus
- Memory bus
If you hear someone talking about the bus in a PC, chances
are good that he or she is referring to the I/O bus,
which also is called the expansion slot bus. Whatever
name it goes by, this bus is the main system bus and the one
over which most data flows. The I/O bus is the highway for
most data in your system. Anything that goes to or from any
device--including your video system, disk drives, and
printer--travels over this bus. The busiest I/O pathway
typically is to and from your video card.
Because the I/O bus is the primary bus in your computer
system, it is the main focus of discussion in this chapter.
The other buses deserve some attention, however, and they are
covered in the following sections.
The Processor Bus
The processor bus is the communication pathway
between the CPU and immediate support chips. These support
chips are usually called the chipset in modern systems.
This bus is used to transfer data between the CPU and the main
system bus, for example, or between the CPU and an external
memory cache. Figure 5.1 shows how this bus fits into a
typical PC system.
FIG.
5.1 The processor bus.
Most systems have an external cache for the CPU; these
caches have typically been employed in all systems that use
the Pentium, Pentium MMX, Pentium Pro, and Pentium II
chips.
Because the purpose of the processor bus is to get
information to and from the CPU at the fastest possible speed,
this bus operates at a much faster rate than any other bus in
your system; no bottleneck exists here. The bus consists of
electrical circuits for data, for addresses (the address bus,
which is discussed in the following section), and for control
purposes. In a Pentium-based system, the processor bus has 64
data lines, 32 address lines, and associated control lines.
The Pentium Pro and Pentium II have 36 address lines, but
otherwise are the same as the Pentium and Pentium MMX.
The processor bus operates at the same base clock rate as
the CPU does externally. This can be misleading as most CPUs
these days run internally at a higher clock rate than they do
externally. For example, a Pentium 100 system has a Pentium
CPU running at 100MHz internally, but only 66.6MHz externally.
A Pentium 133, Pentium 166, and even a Pentium Pro 200 also
run the processor external bus at 66.6MHz. In most newer
systems, the actual processor speed is some multiple (1.5x,
2x, 2.5x, 3x, and so on) of the processor bus. For more
information on this, see "Processor Speed Ratings" in Chapter
6, "Microprocessor Types and Specifications."
The processor bus is tied to the external processor pin
connections and can transfer one bit of data per data line
every one or two clock cycles. Thus, a Pentium, Pentium Pro,
or Pentium II can transfer 64 bits of data at a time.
To determine the transfer rate for the processor bus, you
multiply the data width (64 bits for a Pentium, Pentium Pro,
or Pentium II) by the clock speed of the bus (the same as the
base or unmultiplied clock speed of the CPU). If you are using
a Pentium, Pentium MMX, Pentium Pro, or Pentium II chip that
runs at a 66MHz motherboard speed, and it can transfer a bit
of data each clock cycle on each data line, you have a maximum
instantaneous transfer rate of 528M/sec. You get this result
by using the following formula: 66MHz x 64 bits =
4,224Mbit/sec 4,224Mbit/sec ÷ 8 = 528M/sec This transfer rate,
often called the bandwidth of the bus, represents a
maximum. Like all maximums, this rate does not represent the
normal operating bandwidth; you should expect much lower
average throughput. Other limiting factors such as chipset
design, memory design and speed, and so on, conspire to lower
the effective average throughput.
The Memory Bus
The memory bus is used to transfer information
between the CPU and main memory--the RAM in your system. This
bus is either a part of the processor bus itself, or in most
cases is implemented separately by a dedicated chipset that is
responsible for transferring information between the processor
bus and the memory bus. Systems that run at mother-board clock
speeds of 16MHz or faster cycle at rates that exceed the
capabilities of standard Dynamic RAM chips. In virtually all
systems that are 16MHz or faster, there will be a special
memory controller chipset that controls the interface between
the faster processor bus and the slower main memory. This
chipset typically is the same chipset that is responsible for
managing the I/O bus. Figure 5.2 shows how the memory bus fits
into your PC.
FIG.
5.2 The memory bus.
The information that travels over the memory bus is
transferred at a much slower rate than the information on the
processor bus. The chip sockets or the slots for memory
SIMMs/DIMMs (Dual Inline Memory Modules) are connected to the
memory bus in much the same way that expansion slots are
connected to the I/O bus.
CAUTION: Notice that the main memory bus is
always the same width as the processor bus. This means that
in a 64-bit system, such as the various Pentium CPUs, you
will have a 64-bit memory bus. This will define the size of
what is called a "bank" of memory. For example, a 486DX4
processor has a 32-bit bus, so the memory in that system
must be added 32 bits at a time for each bank. If you are
using 30-pin (8-bit) SIMMs, then four will be required per
bank; if the system uses 72-pin (32-bit) SIMMs, then only
one has to be added at a time to make up a bank. Pentium
systems are 64-bit and always require two 72-pin (32 bits
each) SIMMs to be added at a time. Some newer systems use
168-pin DIMMs, which are 64 bits each. These compose a
single bank in a 64-bit system.
The Address Bus
The address bus actually is a subset of the
processor and memory buses. In our discussion of the processor
bus, you learned that a Pentium system bus consists of 64 data
lines, 32 address lines (36 in a Pentium Pro or Pentium II),
and a few control lines. These address lines constitute the
address bus; in most block diagrams, this bus is actually
considered a part of the processor and memory buses.
The address bus is used to indicate what address in memory
or what address on the system bus are to be used in a data
transfer operation. The address bus indicates precisely where
the next bus transfer or memory transfer will occur. The size
of the memory bus also controls the amount of memory that the
CPU can address directly.
The Need for Expansion Slots
The I/O bus or expansion slots are what enables your CPU to
communicate with peripheral devices. The bus and its
associated expansion slots are needed because basic systems
cannot possibly satisfy all the needs of all the people who
buy them. The I/O bus enables you to add devices to your
computer to expand its capabilities. The most basic computer
components, such as sound cards and video cards, can be
plugged into expansion slots; you also can plug in more
specialized devices, such as network interface cards, SCSI
host adapters, and others.
NOTE: In most modern PC systems, a variety of
basic peripheral devices are built into the motherboard.
Most systems today have at least dual (primary and
secondary) IDE controllers, a floppy controller, two serial
ports, and a parallel port directly built into the
motherboard. This is normally contained on a single chip
called a Super I/O chip. Many will even add more items such
as an integrated mouse port, video adapter, SCSI host
adapter, or network interface also built into the
mother-board; in such a system, an expansion slot on the I/O
bus is probably not even needed. Never-theless, these
built-in controllers and ports still use the I/O bus to
communicate with the CPU. In essence, even though they are
built in, they act as if they are cards plugged into the
system's bus slots.
Although some PC systems provide only a single expansion
slot, most provide up to eight slots on the motherboard. This
slot typically is called a riser card slot. The riser
card that plugs into it in turn has expansion slots on its
sides. Standard adapter cards are installed in the riser card,
meaning that the adapter cards end up being parallel to the
motherboard rather than perpendicular to it.
Riser cards are used when a vendor wants to produce a
computer that is shorter in height than normal. These
computers usually are called Slimline, Low
Profile, or sometimes even pizza-box systems. Even
though this type of configuration may seem to be odd, the
actual bus used in these systems is the same kind used in
normal computer systems; the only difference is the use of the
riser card.
I usually recommend avoiding the Low Profile or Slimline
systems that have what is called an LPX form factor.
This refers to the shape of the board. Replacement LPX
motherboards with riser cards that match the case for a given
system are difficult to find. However, a newer form factor
recently developed by Intel called NLX incorporates a
Low Profile design, while at the same time enjoying growing
industry support.
Bus Mastering
Newer bus types use a technology called bus
mastering to speed up the system. In essence, a bus
master is an adapter with its own processor that can
execute operations independently of the CPU. To work properly,
bus-mastering technology relies on an arbitration unit, most
often called an integrated system peripheral (ISP)
chip. The ISP enables a bus-mastered board to temporarily
take exclusive control of the system, as though the board were
the entire system. Because the board has exclusive control of
the system, it can perform operations very quickly. A
bus-mastering hard drive controller, for example, achieves
much greater data throughput with a fast drive than can
controller cards that are not bus-mastered.
The ISP determines which device gains control by using a
four-level order of priority:
- System-memory refresh
- The CPU itself
- Bus masters
- DMA transfers
A bus-mastering adapter board notifies the ISP when it
wants control of the system. At the earliest possible time
(after the higher priorities have been satisfied), the ISP
hands control over to the bus-mastered board. The board, in
turn, has built-in circuitry to keep it from taking over the
system for periods of time that would interfere with
first-priority operations, such as memory refresh.
Types of I/O Buses
Since the introduction of the first PC, many I/O buses have
been introduced. The reason is quite simple: Faster I/O speeds
are necessary for better system performance. This need for
higher performance involves three main areas:
- Faster CPUs
- Increasing software demands
- Greater multimedia requirements
Each of these areas requires the I/O bus to be as fast as
possible. Surprisingly, virtually all PC systems shipped today
still incorporate the same basic bus architecture as the 1984
vintage IBM PC/AT. However, most of these systems now also
include a second high-speed local I/O bus such as VL-Bus or
PCI, which offer much greater performance for adapters that
need it.
One of the primary reasons why new I/O-bus structures have
been slow in coming is compatibility--that old Catch-22 that
anchors much of the PC industry to the past. One of the
hallmarks of the PC's success is its standardization. This
standardization spawned thousands of third-party I/O cards,
each originally built for the early bus specifications of the
PC. If a new high-performance bus system is introduced, it
often has to be compatible with the older bus systems so that
the older I/O cards do not become obsolete. Therefore, bus
technologies seem to evolve rather than make quantum leaps
forward.
You can identify different types of I/O buses by their
architecture. The main types of I/O architecture are:
- ISA
- PCI Local Bus
- PC Card (formerly PCMCIA)
- FireWire (IEEE-1394)
- Micro Channel Architecture (MCA)
- EISA
- Universal Serial Bus (USB)
- VESA Local Bus (VL-Bus)
The differences among these buses consist primarily of the
amount of data that they can transfer at one time and the
speed at which they can do it. Each bus architecture is
implemented by a chipset that is connected to the processor
bus. Typically, this chipset also controls the memory bus
(refer to Figure 5.2). The following sections describe the
different types of PC buses.
The ISA Bus
ISA, which is an acronym for Industry Standard
Architecture, is the bus architecture that was introduced
as an 8-bit bus with the original IBM PC in 1981 and later
expanded to 16 bits with the IBM PC/AT in 1984. ISA is the
basis of the modern personal computer and the primary
architecture used in the vast majority of PC systems on the
market today. It may seem amazing that such a seemingly
antiquated architecture is used in today's high-performance
systems, but this is true for reasons of reliability,
affordability, and compatibility, plus this old bus is still
faster than many of the peripherals that we connect to it!
Two versions of the ISA bus exist, based on the number of
data bits that can be transferred on the bus at a time. The
older version is an 8-bit bus; the newer version is a 16-bit
bus. The original 8-bit version ran at 4.77MHz in the PC and
XT. The 16-bit version used in the AT ran at 6MHz and then
8MHz. Later, the industry as a whole agreed on an 8.33MHz
maximum standard speed for 8- and 16-bit versions of the ISA
bus for backward compatibility. Some systems have the ability
to run the ISA bus faster than this, but some adapter cards
will not function properly at higher speeds. ISA data
transfers require anywhere from two to eight cycles.
Therefore, the theoretical maximum data rate of the ISA bus is
about 8M/sec, as the following formula shows: 8MHz x 16 bits =
128Mbit/sec
128Mbit/sec ÷ 2 cycles = 64Mbit/sec 64Mbit/sec ÷ 8 = 8M/sec
The bandwidth of the 8-bit bus would be half this figure
(4M/sec). Remember, however, that these figures are
theoretical maximums; because of I/O bus protocols, the
effective bandwidth is much lower--typically by almost half.
Even so, at 8M/sec, the ISA bus is still faster than many of
the peripherals we connect to it.
The 8-Bit ISA Bus
This bus architecture is used in the original IBM PC
computers. Although virtually nonexistent in new systems
today, this architecture still exists in hundreds of thousands
of PC systems in the field. Physically, the 8-bit ISA
expansion slot resembles the tongue-and-groove system that
furniture makers once used to hold two pieces of wood
together. It is specifically called a Card/Edge
connector. An adapter card with 62 contacts on its bottom
edge plugs into a slot on the motherboard that has 62 matching
contacts. Electronically, this slot provides eight data lines
and 20 addressing lines, enabling the slot to handle 1M of
memory.
Figure 5.3 describes the pinouts for the 8-bit ISA bus.
FIG.
5.3 Pinouts for the 8-bit ISA
bus.
Figure 5.4 shows how these pins are oriented in the
expansion slot.
FIG.
5.4 The 8-bit ISA bus connector.
Although the design of the bus is simple, IBM waited until
1987 to publish full specifications for the timings of the
data and address lines, so in the early days of PC
compatibles, manufacturers had to do their best to figure out
how to make adapter boards. This problem was solved, however,
as PC-compatible personal computers became more widely
accepted as the industry standard and manufacturers had more
time and incentive to build adapter boards that worked
correctly with the bus.
The dimensions of 8-bit ISA adapter cards are as follows:
4.2 inches (106.68mm) high
13.13 inches (333.5mm) long 0.5 inch (12.7mm) wide
The 16-Bit ISA Bus
IBM threw a bombshell on the PC world when it introduced
the AT with the 286 processor in 1984. This processor had a
16-bit data bus, which meant that communications between the
processor and the motherboard as well as memory would now be
16 bits wide instead of only 8 bits wide.
Although this processor could have been installed on a
motherboard with only an 8-bit I/O bus, that would have meant
a huge sacrifice in the performance of any adapter cards or
other devices installed on the bus. The introduction of the
286 chip posed a problem for IBM in relation to its next
generation of PCs. Should the company create a new I/O bus and
associated expansion slots, or should it try to come up with a
system that could support both 8- and 16-bit cards? IBM opted
for the latter solution, and the PC/AT was introduced with a
set of expansion slots with 16-bit extension connectors. You
can plug an 8-bit card into the forward part of the slot or a
16-bit card into both parts of the slot.
NOTE: The expansion slots for the 16-bit ISA
bus also introduced access keys to the PC environment. An
access key is a cutout or notch in an adapter card that fits
over a corresponding tab in the connector into which the
adapter card is inserted. Access keys typically are used to
keep adapter cards from being inserted into a connector
improperly.
The extension connector in each 16-bit expansion slot adds
36 connector pins to carry the extra signals necessary to
implement the wider data path. In addition, two of the pins in
the 8-bit portion of the connector were changed. These two
minor changes do not alter the function of 8-bit cards.
Figure 5.5 describes the pinouts for the full 16-bit ISA
expansion slot.
FIG.
5.5 Pinouts for the 16-bit ISA
bus.
Figure 5.6 shows the orientation and relation of 8-bit and
16-bit ISA bus slots.
FIG.
5.6 The 8-bit and 16-bit ISA bus
connectors.
The extended 16-bit slots physically interfere with some
8-bit adapter cards that have a skirt--an extended area
of the card that drops down toward the motherboard just after
the connector. To handle these cards, IBM left two expansion
ports in the PC/AT without the 16-bit extensions. These slots,
which are identical to the expansion slots in earlier systems,
can handle any skirted PC or XT expansion card. This is not a
problem today, as no skirted 8-bit cards have been
manufactured for years.
NOTE: 16-bit ISA expansion slots were
introduced in 1984. Since then, virtually every manufacturer
of 8-bit expansion cards have designed them without
drop-down skirts so that they fit properly in 16-bit slots.
Most new systems do not have any 8-bit only slots, because a
properly designed 8-bit card will work in any 16-bit slot.
The dimensions of a typical AT expansion board are as
follows: 4.8 inches (121.92mm) high
13.13 inches (333.5mm) long 0.5 inch (12.7mm) wide Two
heights actually are available for cards that are commonly
used in AT systems: 4.8 inches and 4.2 inches (the height of
older PC-XT cards). The shorter cards became an issue when IBM
introduced the XT Model 286. Because this model has an AT
motherboard in an XT case, it needs AT-type boards with the
4.2-inch maximum height. Most board makers trimmed the height
of their boards; many manufacturers now make only 4.2-inch
tall (or less) boards so that they will work in systems with
either profile.
32-Bit Buses
After 32-bit CPUs became available, it was some time before
32-bit bus standards became available. Before MCA and EISA
specs were released, some vendors began creating their own
proprietary 32-bit buses, which were extensions of the ISA
bus. Although the proprietary buses were few and far between,
they do still exist. The expanded portions of the bus
typically are used for proprietary memory expansion or video
cards. Because the systems are proprietary (meaning that they
are nonstandard), pinouts and specifications are not
available.
The Micro Channel Bus
The introduction of 32-bit chips meant that the ISA bus
could not handle the power of another new generation of CPUs.
The 386DX chips can transfer 32 bits of data at a time, but
the ISA bus can handle a maximum 16 bits. Rather than extend
the ISA bus again, IBM decided to build a new bus; the result
was the MCA bus. MCA (an acronym for Micro Channel
Architecture) is completely different from the ISA bus and
is technically superior in every way.
IBM not only wanted to replace the old ISA standard but
also to receive royalties on it; the company required vendors
that licensed the new MCA bus to pay IBM royalties for using
the ISA bus in all previous systems. This requirement led to
the development of the competing EISA bus (see the next
section on the EISA Bus) and hindered acceptance of the MCA
bus. Another reason why MCA has not been adopted universally
for systems with 32-bit slots is that adapter cards designed
for ISA systems do not work in MCA systems.
NOTE: The MCA bus is not compatible with the
older ISA bus, so cards designed for the ISA bus do not work
in an MCA system.
MCA runs asynchronously with the main processor, meaning
that fewer possibilities exist for timing problems among
adapter cards plugged into the bus.
MCA systems produced a new level of ease of use, as anyone
who has set up one of these systems can tell you. An MCA
system has no jumpers and switches--neither on the motherboard
nor on any expansion adapter. You don't need an electrical
engineering degree to plug a card into a PC.
The MCA bus also supports bus mastering. Through
implementing bus mastering, the MCA bus provides significant
performance improvements over the older ISA buses. (Bus
mastering is also implemented in the EISA bus. In the MCA bus
mastering implementation, any bus mastering devices can
request unobstructed use of the bus in order to communicate
with another device on the bus. The request is made through a
device known as the Central Arbitration Control Point
(CACP). This device arbitrates the competition for the
bus, making sure all devices have access and that no single
device monopolizes the bus.
Each device is given a priority code to ensure that order
is preserved within the system. The main CPU is given the
lowest priority code. Memory refresh has the highest priority,
followed by the DMA channels, and then the bus masters
installed in the I/O slots. One exception to this is when an
NMI (non-maskable interrupt) occurs. In this instance, control
returns to the CPU immediately.
The MCA specification provides for four adapter sizes,
which are described in Table 5.1.
Table 5.1 Physical Sizes of MCA Adapter
Cards
Adapter Type |
Height (in Inches) |
Length (in Inches) |
Type 3 |
3.475 |
12.3 |
Type 3 half |
3.475 |
6.35 |
Type 5 |
4.825 |
13.1 |
Type 9 |
9.0 |
13.1 |
Four types of slots are involved in the MCA design:
- 16-bit
- 16-bit with video extensions
- 16-bit with memory-matched extensions
- 32-bit
The sixth edition of this book, included on the CD-ROM, has
detailed information about each of these cards and what
systems they can be found in. IBM still has all of the
technical reference manuals for MCA available; however,
development has stopped for MCA devices due to the other
faster and more feature-rich buses available today.
The EISA Bus
EISA is an acronym for Extended Industry Standard
Architecture. This standard was announced in September
1988 as a response to IBM's introduction of the MCA bus--more
specifically, to the way that IBM wanted to handle licensing
of the MCA bus. Vendors did not feel obligated to pay
retroactive royalties on the ISA bus, so they turned their
backs on IBM and created their own buses.
The EISA standard was developed primarily by Compaq, and
was intended as being their way of taking over future
development of the PC bus away from IBM. Compaq knew that
nobody would clone their bus if they were the only company
that had it, so they essentially gave the design away to other
leading manufacturers. They formed the EISA Committee, a
non-profit organization designed specifically to control
development of the EISA bus. Very few EISA adapters were ever
developed. Those that were developed centered mainly around
disk array controllers and server type network cards.
The EISA bus provides 32-bit slots for use with 386DX or
higher systems. The EISA slot enables manufacturers to design
adapter cards that have many of the capabilities of MCA
adapters, but the bus also supports adapter cards created for
the older ISA standard. EISA provides markedly faster hard
drive throughput when used with devices such as SCSI
bus-mastering hard drive controllers. Compared with 16-bit ISA
system architecture, EISA permits greater system expansion
with fewer adapter conflicts.
The EISA bus adds 90 new connections (55 new signals)
without increasing the physical connector size of the 16-bit
ISA bus. At first glance, the 32-bit EISA slot looks much like
the 16-bit ISA slot. The EISA adapter, however, has two rows
of connectors. The first row is the same kind used in 16-bit
ISA cards; the other, thinner row extends from the 16-bit
connectors. This means that ISA cards can still be used in
EISA bus slots. Although this compatability was not enough to
ensure the popularity of EISA buses, it is a feature that was
carried over into the newer VL-bus standard. The physical
specifications of an EISA card are as follows: 5 inches
(127mm) high
13.13 inches (333.5mm) long 0.5 inches (12.7mm) wide The
EISA bus can handle up to 32 bits of data at an 8.33MHz cycle
rate. Most data transfers require a minimum of two cycles,
although faster cycle rates are possible if an adapter card
provides tight timing specifications. The maximum bandwidth on
the bus is 33M/sec, as the following formula shows: 8.33MHz x
32 bits = 266.56Mbit/sec 266.56Mbit/sec ÷ 8 = 33.32M/sec Data
transfers through an 8- or 16-bit expansion card across the
bus would be reduced appropriately. Remember, however, that
these figures represent theoretical maximums. Wait states,
interrupts, and other protocol factors can reduce the
effective bandwidth--typically, by half.
Figure 5.7 describes the pinouts for the EISA bus.
FIG.
5.7 Pinouts for the EISA bus. Figure 5.8
shows the locations of the pins.
FIG.
5.8 The card connector for the EISA
bus.
Automated Setup
EISA systems also use an automated setup to deal with
adapter-board interrupts and addressing issues. These issues
often cause problems when several different adapter boards are
installed in an ISA system. EISA setup software recognizes
potential conflicts and automatically configures the system to
avoid them. EISA does, however, enable you to do your own
troubleshooting, as well as to configure the boards through
jumpers and switches. This concept was not new to EISA; IBM's
MCA bus also supported configuration via software. Another new
feature of EISA systems is IRQ sharing, meaning that multiple
bus cards can share a single interrupt. This feature has also
been implemented in PCI bus cards.
NOTE: Although automated setup traditionally
has not been available in ISA systems, it is now available
with Plug and Play (PnP) systems and components. PnP systems
are discussed toward the end of this chapter in the section
"Plug and Play Systems."
Local Buses
The I/O buses discussed so far (ISA, MCA, and EISA) have
one thing in common: relatively slow speed. This speed
limitation is a carryover from the days of the original PC,
when the I/O bus operated at the same speed as the processor
bus. As the speed of the processor bus increased, the I/O bus
realized only nominal speed improvements, primarily from an
increase in the bandwidth of the bus. The I/O bus had to
remain at a slower speed, because the huge installed base of
adapter cards could operate only at slower speeds.
Figure 5.9 shows a conceptual block diagram of the buses in
a computer system.
FIG.
5.9 Bus layout in a traditional
PC.
The thought of a computer system running slower than it
could is very bothersome to some computer users. Even so, the
slow speed of the I/O bus is nothing more than a nuisance in
most cases. You don't need blazing speed to communicate with a
keyboard or a mouse, for example; you gain nothing in
performance. The real problem occurs in subsystems in which
you need the speed, such as video and disk controllers.
The speed problem became acute when graphical user
interfaces (such as Windows) became prevalent. These systems
required the processing of so much video data that the I/O bus
became a literal bottleneck for the entire computer system. In
other words, it did little good to have a CPU that was capable
of 66MHz speed if you could put data through the I/O bus at a
rate of only 8MHz.
An obvious solution to this problem is to move some of the
slotted I/O to an area where it could access the faster speeds
of the processor bus--much the same way as the external cache.
Figure 5.10 shows this arrangement.
FIG.
5.10 How a local bus works.
This arrangement became known as local bus, because
external devices (adapter cards) now could access the part of
the bus that was local to the CPU--the processor bus.
Physically, the slots provided to tap this new configuration
would need to be different from existing bus slots, to prevent
adapter cards designed for slower buses from being plugged
into the higher bus speeds that this design made
accessible.
It is interesting to note that the very first 8-bit and
16-bit ISA buses were a form of Local Bus architecture. These
systems had the processor bus as the main bus, and everything
ran at full processor speeds. When ISA systems ran faster than
8MHz, the main ISA bus had to be decoupled from the processor
bus since expansion cards, memory, and so on could not keep
up. In 1992, an extension to the ISA bus called the VESA
Local Bus started showing up on PC systems, indicating a
return to Local Bus architecture.
NOTE: A system does not have to have a
local-bus expansion slot to incorporate local-bus
technology; instead, the local-bus device can be built
directly into the motherboard. (In such a case, the
local-bus-slotted I/O shown in Figure 5.11 would in fact be
built-in I/O.) This built-in approach to local bus is the
way the first local-bus systems were designed.
Local-bus solutions do not replace earlier standards, such
as ISA; they are designed as an extension to existing
standards. Therefore, a typical system is based on ISA or EISA
and has one or more local-bus slots available as well. Older
cards still are compatible with the system, but high-speed
adapter cards can also take advantage of the local-bus
slots.
Local-bus systems are especially popular with users of
Windows and OS/2, because these slots are used for special
32-bit video accelerator cards that greatly speed the
repainting of the graphics screens used in those operating
systems. The performance of Windows and OS/2 suffers greatly
from bottlenecks in even the best VGA cards connected to an
ISA or EISA bus.
VESA Local Bus
The VESA Local Bus was the most popular local bus design
from its debut in August 1992 through 1994. It was created by
the VESA committee, a non-profit organization founded by NEC
to further develop video display and bus standards. In a
similar fashion to how EISA evolved, NEC had done most of the
work on the VL-bus (as it would be called) and, after founding
the non-profit VESA committee, they turned over future
development to VESA. At first, the local-bus slot seemed
primarily designed to be used for video cards. Improving video
performance was a top priority at NEC to help sell their
high-end displays as well as their own PC systems. By 1991,
video performance had become a real bottleneck in most PC
systems.
The Video Electronics Standards Association (VESA)
developed a standardized local-bus specification known as
VESA Local Bus or simply VL-Bus. As in earlier
local-bus implementations, the VL-Bus slot offers direct
access to system memory at the speed of the processor itself.
The VL-Bus can move data 32 bits at a time, enabling data to
flow between the CPU and a compatible video subsystem or hard
drive at the full 32-bit data width of the 486 chip. The
maximum rated throughput of the VL-Bus is 128M to 132M/sec. In
other words, local bus went a long way toward removing the
major bottlenecks that existed in earlier bus
configurations.
Additionally, VL-Bus offers manufacturers of hard-drive
interface cards an opportunity to overcome another traditional
bottleneck: the rate at which data can flow between the hard
drive and the CPU. The average 16-bit IDE drive and interface
can achieve throughput of up to 5M/sec, whereas VL-Bus hard
drive adapters for IDE drives are touted as providing
throughput of as much as 8M/sec. In real-world situations, the
true throughput of VL-Bus hard drive adapters is somewhat less
than 8M/sec, but VL-Bus still provides a substantial boost in
hard-drive performance.
Despite all the benefits of the VL-Bus (and, by extension,
of all local buses), this tech-nology has a few drawbacks,
which are described in the following list:
- Dependence on a 486 CPU. The VL-Bus inherently is
tied to the 486 processor bus. This bus is quite different
from that used by Pentium processors (and probably from
those that will be used by future CPUs). A VL-Bus that
operates at the full- rated speed of a Pentium has not been
developed, although stopgap measures (such as stepping down
speed or developing bus bridges) are available.
Unfortunately, these result in poor performance. Some
systems have been developed with both VL-Bus and PCI slots,
but because of design compromises, performance often
suffers.
- Speed limitations. The VL-Bus specification
provides for speeds of up to 66MHz on the bus, but the
electrical characteristics of the VL-Bus connector limit an
adapter card to no more than 40 to 50MHz. In practice,
running the VL-Bus at speeds over 33MHz causes many
problems, so 33MHz has become the acceptable speed limit.
Systems that use faster processor bus speeds must buffer and
step down the clock on the VL-Bus or add wait states. Note
that if the main CPU uses a clock modifier (such as the kind
that doubles clock speeds), the VL-Bus uses the unmodified
CPU clock speed as its bus speed.
- Electrical limitations. The processor bus has
very tight timing rules, which may vary from CPU to CPU.
These timing rules were designed for limited loading on the
bus, meaning that the only elements originally intended to
be connected to the local bus are elements such as the
external cache and the bus controller chips. As you add more
circuitry, you increase the electrical load. If the local
bus is not implemented correctly, the additional load can
lead to problems such as loss of data integrity and timing
problems between the CPU and the VL-Bus cards.
- Card limitations. Depending on the electrical
loading of a system, the number of VL-Bus cards is limited.
Although the VL-Bus specification provides for as many as
three cards, this can be achieved only at clock rates of up
to 40MHz with an otherwise low system-board load. As the
system-board load increases and the clock rate increases,
the number of cards supported decreases. Only one VL-Bus
card can be supported at 50MHz with a high system-board
load. In practice, these limits could not usually be reached
without problems.
The VL-Bus did not seem to be a well-engineered concept.
The design was simple indeed--just take the pins from the 486
processor and run them out to a card connector socket. In
other words, the VL-Bus is essentially the raw 486 processor
bus. This allowed a very inexpensive design, since no
additional chipsets or interface chips were required. A
motherboard designer could add VL-Bus slots to their 486
motherboards very easily and at a very low cost. This is why
these slots appeared on virtually all 486 system designs
overnight.
Unfortunately, the 486 processor bus was not designed to
have multiple devices (called loads) plugged into it at
one time. Problems arose with timing glitches caused by the
capacitance introduced into the circuit by different cards.
Since the VL-Bus ran at the same speed as the processor bus,
different processor speeds meant different bus speeds, and
full compatibility was difficult to achieve. Although the
VL-Bus could be adapted to other processors, including the 386
or even the Pentium, it was designed for the 486, and worked
best as a 486 solution only. Despite the low cost, after a new
bus called PCI (Peripheral Component Interconnect)
appeared, VL-Bus fell into disfavor very quickly. It never did
catch on with Pentium systems, and there is little or no
further development of the VL-Bus in the PC industry. I would
not recommend purchasing VL-Bus cards or systems today.
For a used system, or as an inexpensive upgrade for an
older system, VL-Bus might be appropriate and can provide an
acceptable solution for high-speed computing.
Physically, the VL-Bus slot is an extension of the slots
used for whatever type of base system you have. If you have an
ISA system, the VL-Bus is positioned as an extension of your
existing 16-bit ISA slots. Likewise, if you have an EISA
system or MCA system, the VL-Bus slots are extensions of those
existing slots. Figure 5.11 shows how the VL-Bus slots could
be situated in an ISA system. The VESA extension has 112
contacts and uses the same physical connector as the MCA
bus.
The VL-Bus adds a total 116 pin locations to the bus
connectors that your system already has. Table 5.2 lists the
pinouts for only the VL-Bus connector portion of the total
connector. (For pins for which two purposes are listed, the
second purpose applies when the card is in 64-bit transfer
mode.)
Table 5.2 Pinouts for the VL-Bus
Pin |
Signal Name |
Pin |
Signal Name |
B1 |
Data 0 |
A1 |
Data 1 |
B2 |
Data 2 |
A2 |
Data 3 |
B3 |
Data 4 |
A3 |
Ground |
B4 |
Data 6 |
A4 |
Data 5 |
B5 |
Data 8 |
A5 |
Data 7 |
B6 |
Ground |
A6 |
Data 9 |
B7 |
Data 10 |
A7 |
Data 11 |
B8 |
Data 12 |
A8 |
Data 13 |
B9 |
VCC |
A9 |
Data 15 |
B10 |
Data 14 |
A10 |
Ground |
B11 |
Data 16 |
A11 |
Data 17 |
B12 |
Data 18 |
A12 |
VCC |
B13 |
Data 20 |
A13 |
Data 19 |
B14 |
Ground |
A14 |
Data 21 |
B15 |
Data 22 |
A15 |
Data 23 |
B16 |
Data 24 |
A16 |
Data 25 |
B17 |
Data 26 |
A17 |
Ground |
B18 |
Data 28 |
A18 |
Data 27 |
B19 |
Data 30 |
A19 |
Data 29 |
B20 |
VCC |
A20 |
Data 31 |
B21 |
Address 31 or Data 63 |
A21 |
Address 30 or Data 62 |
B22 |
Ground |
A22 |
Address 28 or Data 60 |
B23 |
Address 29 or Data 61 |
A23 |
Address 26 or Data 58 |
B24 |
Address 27 or Data 59 |
A24 |
Ground |
B25 |
Address 25 or Data 57 |
A25 |
Address 24 or Data 56 |
B26 |
Address 23 or Data 55 |
A26 |
Address 22 or Data 54 |
B27 |
Address 21 or Data 53 |
A27 |
VCC |
B28 |
Address 19 or Data 51 |
A28 |
Address 20 or Data 52 |
B29 |
Ground |
A29 |
Address 18 or Data 50 |
B30 |
Address 17 or Data 49 |
A30 |
Address 16 or Data 48 |
B31 |
Address 15 or Data 47 |
A31 |
Address 14 or Data 46 |
B32 |
VCC |
A32 |
Address 12 or Data 44 |
B33 |
Address 13 or Data 45 |
A33 |
Address 10 or Data 42 |
B34 |
Address 11 or Data 43 |
A34 |
Address 8 or Data 40 |
B35 |
Address 9 or Data 41 |
A35 |
Ground |
B36 |
Address 7 or Data 39 |
A36 |
Address 6 or Data 38 |
B37 |
Address 5 or Data 37 |
A37 |
Address 4 or Data 36 |
B38 |
Ground |
A38 |
Write Back |
B39 |
Address 3 or Data 35 |
A39 |
Byte Enable 0 or 4 |
B40 |
Address 2 or Data 34 |
A40 |
VCC |
B41 |
Unused or LBS64# |
A41 |
Byte Enable 1 or 5 |
B42 |
Reset |
A42 |
Byte Enable 2 or 6 |
B43 |
Data/Code Status |
A43 |
Ground |
B44 |
Memory-I/O Status or Data 33 |
A44 |
Byte Enable 3 or 7 |
B45 |
Write/Read Status or Data 32 |
A45 |
Address Data Strobe |
B46 |
Access key |
A46 |
Access key |
B47 |
Access key |
A47 |
Access key |
B48 |
Ready Return |
A48 |
Local Ready |
B49 |
Ground |
A49 |
Local Device |
B50 |
IRQ 9 |
A50 |
Local Request |
B51 |
Burst Ready |
A51 |
Ground |
B52 |
Burst Last |
A52 |
Local Bus Grant |
B53 | |